Sign-Aware Arithmetic Unit for Compact DOT and FMA Processing
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Solution Overview
Problem
Conventional FMA arithmetic units struggle to efficiently perform batch addition in DOT operations due to the indeterminate nature of the accumulated value's sign, leading to difficulties in executing both FMA and DOT operations simultaneously without increasing circuit area.
Innovation Solution
An arithmetic unit that determines whether addition or subtraction is effective based on the elements and addend, performs digit alignment, and calculates the product subtotal considering a bias value to ensure accurate addition or subtraction, enabling simultaneous execution of FMA and DOT operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional FMA arithmetic unit performs batch addition in DOT operation, then operation efficiency improves, but circuit area increases
Solution Approach 1:
The arithmetic unit is designed to perform both FMA operations and DOT operations using the same circuit structure. The control unit determines the operation type and configures the arithmetic unit accordingly, allowing a single circuit to serve multiple functions without requiring separate dedicated circuits for each operation type.
Solution Approach 2:
The arithmetic unit dynamically switches between FMA and DOT operation modes based on control signals. The control unit adjusts the operation mode, number of addends, and accumulation behavior according to the specific operation requirements, enabling the same hardware to adapt to different computational tasks efficiently.
2Speed
If conventional FMA arithmetic unit determines addition or subtraction early, then processing speed improves, but accuracy deteriorates due to sign uncertainty in DOT operation
Solution Approach 1:
The control unit performs preliminary determination of whether addition or subtraction should be executed by analyzing the signs of the accumulated value and addend before the actual arithmetic operation. This early determination allows the arithmetic unit to configure the correct operation mode in advance, improving processing speed without compromising accuracy.
Solution Approach 2:
The system uses feedback from the sign bits of the accumulated value and addend to dynamically determine the operation type. The control unit continuously monitors the signs and adjusts the operation mode accordingly, ensuring both speed and accuracy by making informed decisions based on real-time data.
3Adaptability or versatility
If separate arithmetic units are mounted for FMA and DOT operations, then operation functionality improves, but circuit area increases
Solution Approach 1:
A single arithmetic unit is designed to handle both FMA and DOT operations through configurable control logic. The control unit receives operation type information and configures the arithmetic unit's behavior accordingly, including the number of addends to process and the accumulation method, thereby eliminating the need for separate dedicated circuits.
Solution Approach 2:
The arithmetic unit is segmented into functional modules that can be independently configured for different operations. The control unit divides the operation into stages (multiplication, addition, accumulation) and configures each stage's behavior based on the operation type, allowing flexible adaptation to both FMA and DOT requirements within a unified structure.
Data Source
AI summary
An arithmetic unit executes a DOT operation, the arithmetic unit including a processor configured to, first determine whether or not an operation of the addition result and the addend is effective subtraction or effective addition, on a basis of the elements and the addend, and perform digit alignment of the addend with respect to a subtotal of the products, second determine whether or not there is a possibility that a value to be output becomes negative, on a basis of the elements, and calculate the product subtotal based on the addition result that becomes a negative or positive value, on a basis of a predetermined bias value and the elements, and calculate an operation result by executing addition of the product subtotal calculated and the addend, on a basis of a determination result of the first determination and a determination result of the second determination.