Sign Extension for Compute-in-Memory Vector-Matrix Multiplication
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Solution Overview
Problem
Existing learning networks face challenges in efficiently handling positive and negative values, particularly in edge devices where space and power consumption are limited, complicating hardware and increasing power consumption.
Innovation Solution
A compute engine with a memory and compute logic performs vector-matrix multiplications by separating positive and negative elements, using a compute-in-memory (CIM) hardware module to efficiently handle both types of values, reducing power consumption and hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware accelerators are used to perform parallel operations for machine learning, then speed and efficiency are improved, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the computation by separating positive and negative values into distinct processing paths. The compute engine divides the vector-matrix multiplication into handling positive elements and negative elements separately, then combines the results. This segmentation allows simpler hardware to handle each subset independently without requiring complex signed arithmetic units for all operations simultaneously.
Solution Approach 2:
The patent extracts the sign information from the computational process by separately identifying and processing positive and negative elements. The compute engine extracts negative values from the input vector and weight matrix, processes them through dedicated paths, and then recombines with positive value processing. This extraction simplifies the hardware by removing the need for complex signed number handling in the core compute units.
2Measurement precision
If positive and negative values are handled in traditional hardware, then computational accuracy is maintained, but power consumption increases
Solution Approach 1:
The compute engine segments the computational workload by processing positive and negative elements separately. This allows the hardware to use simpler, lower-power arithmetic units for each subset rather than requiring complex signed arithmetic for all operations, thereby reducing overall power consumption while maintaining accuracy through separate processing paths.
Solution Approach 2:
The patent extracts negative values from the computation and processes them through dedicated hardware paths that are optimized for this specific subset. By extracting and isolating negative value processing, the system avoids the need for complex signed arithmetic across all operations, reducing power consumption while preserving computational accuracy through specialized handling.
3Volume of moving object
If edge devices are used with limited space, then portability is improved, but hardware capacity is reduced
Solution Approach 1:
The patent applies segmentation by dividing the computational task into separate processing paths for positive and negative values. This allows edge devices with limited hardware resources to implement simpler, more space-efficient compute units that handle each subset independently, rather than requiring complex full-featured hardware, thereby maintaining adaptability within constrained physical dimensions.
Solution Approach 2:
The compute engine applies local quality by providing specialized processing paths tailored to specific subsets of data (positive values vs. negative values). Each path is optimized for its specific subset, allowing edge devices to use simpler, more space-efficient hardware for each local task rather than requiring complex universal hardware, thus maintaining versatility within limited device capacity.
Data Source
AI summary
A compute engine including a memory and compute logic is described. The memory includes storage cells. The compute logic is coupled with the memory and configured to perform a vector matrix multiplication (VMM) of an input vector with data stored in each storage cell. The input vector may include positive element(s) and negative element(s). The compute logic is configured to perform the VMM by: multiplying the positive element(s) with data stored in each storage cell of a first portion of storage cells corresponding to the positive element(s) to provide first product(s); accumulating, as a first output, the first product(s); multiplying the negative element(s) with data stored in each storage cell of a second portion of the storage cells corresponding to the negative element(s) to provide second product(s); accumulating, as a second output, the second product(s); and subtracting the second output from the first output to provide a VMM output.