Signal Buffer Circuit High Resistance Control Lines
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reducing chip size while maintaining high data reliability and low power consumption, particularly due to parasitic capacitance in metal layers causing high power consumption in local control signal lines.
Innovation Solution
The implementation of a signal buffer circuit with internal control signal lines made of materials with higher electrical resistance, such as tungsten or titanium nitride, in a local interconnect layer between the second metal layer and the substrate, which provides a delayed control signal to logic and buffer circuits, reducing parasitic capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffers are provided for each block to prevent undesirable load on global control signal lines, then data reliability is improved, but power consumption increases due to parasitic capacitance between local control signal lines
Solution Approach 1:
The patent changes the material parameter of the control signal line from conventional low-resistance metal to high-resistance materials (tungsten, titanium nitride). This parameter change reduces parasitic capacitance effects and power consumption while maintaining signal integrity and data reliability through the buffer circuits.
Solution Approach 2:
The patent employs composite material structures by using high-resistance materials (tungsten or titanium nitride) for the control signal line in the local interconnect layer, combined with conventional metal layers for other signal paths. This composite approach optimizes both power consumption and signal distribution performance.
2Power
If conventional metal layers are used for control signal lines, then electrical conductivity is improved, but parasitic capacitance increases causing high power consumption
Solution Approach 1:
The patent fundamentally changes the electrical resistance parameter of the control signal line material from low (conventional metal) to high (tungsten, titanium nitride). This parameter inversion reduces parasitic capacitance and associated power losses while maintaining adequate signal transmission through the buffer circuit architecture.
3Area of stationary object
If chip size is reduced, then integration density is improved, but power consumption increases due to higher parasitic capacitance density
Solution Approach 1:
By changing the material parameter to high-resistance materials, the patent reduces parasitic capacitance per unit area. This allows smaller chip sizes with higher integration density without proportionally increasing power consumption, as the high-resistance materials mitigate the capacitive effects that would otherwise scale with density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces power consumption and maintains data reliability by minimizing parasitic capacitance and load on global control signal lines, enabling smaller chip sizes with improved power efficiency.
Implementation Method 1
high power consumption among the local control signal lines may be caused due to parasitic capacitance between the local control signal lines in a metal layer
Implementation Method 2
internal control signal lines made of materials with higher electrical resistance, such as tungsten or titanium nitride
Data Source
AI summary
Apparatuses with a signal line in a semiconductor device are described. An example apparatus includes one or more power supply voltage lines in a first conductive layer, a plurality of transistors and a signal line in a second conductive layer. Each transistor of the plurality of transistors includes an active region disposed in a substrate and a gate electrode above the active region. The signal line in the second conductive layer is below the first conductive layer and above the active regions of the plurality of transistors. The signal line is coupled to the gate electrodes of the plurality of transistors. The signal line has electrical resistance higher than electrical resistance of the power supply voltage line.