Signal Input Buffer Offset Calibration Using Segmented Periods
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Solution Overview
Problem
Conventional signal input buffers in semiconductor memory devices face inefficiencies in offset calibration due to errors in design, manufacturing, and environmental factors, leading to increased time required for calibration.
Innovation Solution
A signal input buffer design with 1st and 2nd buffering blocks, input and output switching blocks, and a code generating circuit that calibrates intrinsic and complementary signals in separate periods, controlling voltage levels and conductances to adjust calibration codes based on signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional single-buffer offset calibration is used, then the calibration process is simple, but the calibration time is excessively long
Solution Approach 1:
The calibration process is divided into two separate calibration periods, with each buffering block performing calibration independently during its designated period. This segmentation allows parallel calibration operations, reducing total calibration time while maintaining manageable complexity through structured division of tasks.
Solution Approach 2:
During the first calibration period, the first buffering block performs offset calibration in advance while the second buffering block prepares for its calibration. This preliminary action ensures that calibration is completed ahead of time, reducing the loss of calibration time without requiring complex simultaneous calibration mechanisms.
2Measurement precision
If calibration code value is changed and set repeatedly, then offset calibration accuracy is improved, but the calibration process time is increased
Solution Approach 1:
The two buffering blocks perform calibration continuously in alternating periods rather than sequentially repeating the same calibration process multiple times. This continuous useful action maintains high calibration accuracy through multiple code adjustments while reducing total calibration time by eliminating idle waiting periods.
Solution Approach 2:
The calibration process uses periodic action with two distinct calibration periods, where each buffering block performs calibration during its designated period. This periodic structure allows repeated code value changes and adjustments to achieve high accuracy while maintaining efficient time utilization through alternating operation cycles.
3Productivity
If differential amplifier with symmetrical components is used, then signal buffering capability is improved, but offset error is generated
Solution Approach 1:
The patent applies parameter changes by adjusting the calibration code values during separate calibration periods to compensate for offset errors in the symmetrical components. This allows the differential amplifier to maintain its high signal buffering capability while correcting manufacturing precision issues through dynamic parameter adjustment rather than changing the fundamental symmetrical structure.
Data Source
AI summary
A signal input buffer includes 1-st and 2-nd buffering blocks; a 1-st input switching block; a 2-nd input switching block; a 1-st output switching block; and a 2-nd output switching block. The signal input buffer buffers a reception signal pair and generates a buffered signal pair, and is capable of operation in a normal mode and a calibration mode, the reception signal pair includes an intrinsic reception signal and a complementary reception signal, the buffered signal pair includes an intrinsic buffered signal and a complementary buffered signal, and the calibration mode includes a 1-st calibration period and a 2-nd calibration period.