Signal Bus via Cell Abutment for MTCMOS Power Control
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Solution Overview
Problem
The addition of sleep transistors to standard cell libraries in integrated circuits increases the height and complexity of logic cells, requires additional routing resources, and can lead to electro-migration issues in Multi-Threshold Complementary Metal Oxide Semiconductor (MTCMOS) circuits, causing layout congestion and reliability problems.
Innovation Solution
An integrated circuit design that forms a signal bus through the cell abutment of logic cells, using a polycrystalline silicon layer to distribute signals, including a sleep signal, which reduces the area and height of logic cells, simplifies routing, and eliminates the need for separate sleep pins, thereby reducing complexity and avoiding electro-migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If sleep transistors are added to standard cell libraries to control power consumption, then power control capability is improved, but logic cell height and area increase by approximately 11%
Solution Approach 1:
The patent merges the sleep signal distribution function into the existing logic cell structure by forming a signal bus through cell abutment. The polycrystalline silicon layer that forms logic cells is extended to create the signal bus, eliminating the need for separate sleep transistor structures and their associated routing resources. This integration reduces the overall area while maintaining power control capability.
2Adaptability or versatility
If sleep transistors are added to standard cell libraries, then power control capability is improved, but device complexity and routing resources increase
Solution Approach 1:
The patent makes the polycrystalline silicon layer serve multiple functions: it forms the logic cells themselves and simultaneously creates the signal bus for distributing sleep signals. This multi-functionality eliminates the need for dedicated sleep transistor structures and separate routing resources, thereby reducing device complexity while maintaining power control capability.
3Adaptability or versatility
If MTCMOS circuits use virtual ground to control power, then power control capability is improved, but electro-migration occurs reducing reliability
Solution Approach 1:
The patent extracts the sleep signal distribution function from the power control mechanism. Instead of using virtual ground that carries pulsed direct current (which causes electro-migration), the invention uses a dedicated signal bus formed by extending the polycrystalline silicon layer to distribute sleep signals. This separates the control signal path from the power path, eliminating electro-migration issues while maintaining power control capability.
4Adaptability or versatility
If separate sleep pins are added to each logic cell, then power control capability is improved, but layout congestion and blockages increase
Solution Approach 1:
The patent merges multiple separate sleep pin functions into a single unified signal bus. By extending the polycrystalline silicon layer to form a continuous signal bus that passes through multiple logic cells, the invention eliminates the need for separate sleep pins in each cell. This integration reduces layout congestion and blockages while maintaining the ability to control power in individual logic cells.
Data Source
AI summary
An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal and to distribute the signal to each of the at least two logic cells.