Signal Development Cache for Memory Read Broadcast Throughput
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Solution Overview
Problem
Memory devices face throughput limitations due to latency differences between signal development and sense amplifier operations, particularly when using a 1:1 mapping of signal development components and sense amplifiers, which can affect latency-sensitive applications.
Innovation Solution
Implementing a signal development cache with a set of cache elements that can be selectively coupled or decoupled from sense amplifiers, allowing for independent signal development and sequential coupling with a selection component to generate output signals, and enabling read broadcast operations across multiple locations in the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a 1:1 mapping of signal development components and sense amplifiers is used, then device complexity is reduced, but throughput is limited due to latency differences
Solution Approach 1:
The patent segments the signal development function by introducing a signal development cache with multiple cache elements that can be selectively coupled to sense amplifiers. This allows the signal development process to be divided into independent stages, with multiple cache elements able to operate in parallel, thereby increasing throughput while maintaining manageable complexity through modular organization
Solution Approach 2:
The patent introduces a temporal dimension to the mapping by implementing selective and sequential coupling between cache elements and sense amplifiers. Instead of a static 1:1 mapping, the system dynamically reconfigures connections over time, allowing a single cache element to serve multiple sense amplifiers at different time intervals, thus increasing throughput without proportionally increasing device complexity
2Reliability
If signal development and sense amplifier operations are performed sequentially, then reliability is improved, but latency increases
Solution Approach 1:
The patent implements preliminary signal development by developing signals in the signal development cache before they are needed by the sense amplifiers. This preliminary action allows the signal to be prepared in advance and held in the cache, ensuring reliability through proper signal development while reducing latency by having the signal ready when the sense amplifier is prepared to receive it
Solution Approach 2:
The signal development cache acts as an intermediary between the memory array and the sense amplifiers. This intermediary structure allows signal development operations to be decoupled from sense amplifier operations in time, enabling reliable signal development to complete before the sense amplifier needs the signal, thereby maintaining reliability while reducing the critical path latency
Data Source
AI summary
Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.