Signal Processing Chip Unified Protocol Interconnect
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing chip-to-chip interconnect technologies experience increased signal processing delay and data transmission overhead due to protocol conversion and queuing, leading to reduced processing performance.
Innovation Solution
A signal processing chip design that includes sampling and transmission mechanisms to sample signals on a signal line and transmit data frames with predetermined conditions, reducing the need for protocol conversion and minimizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If protocol conversion is performed in chip-to-chip interconnect, then signal compatibility between different chips is improved, but signal processing delay increases
Solution Approach 1:
The patent extracts and eliminates the protocol conversion process from the chip-to-chip interconnect system. By using a unified protocol across all chips, the complex protocol conversion layer is removed, directly reducing signal processing delay while maintaining compatibility through standardization rather than conversion.
Solution Approach 2:
Instead of converting protocols to achieve compatibility (traditional approach), the patent inverts the approach by enforcing a unified protocol from the beginning. This prevents the need for conversion entirely, transforming the problem from one of adaptation to one of standardization.
2Reliability
If protocol conversion with transport layer and data link layer is employed, then communication reliability is improved, but the amount of transfer data increases due to large overhead
Solution Approach 1:
The patent extracts and removes the transport layer and data link layer overhead from the communication protocol. By designing a simplified protocol that operates directly at the physical layer or application layer, unnecessary protocol headers and control information are eliminated, reducing the amount of transfer data while maintaining essential communication reliability.
Solution Approach 2:
The patent changes the protocol structure parameters by eliminating intermediate layers. Instead of using complex multi-layer protocols with large headers, it adopts a streamlined protocol with minimized overhead, changing the fundamental parameters of data framing and control information to reduce total data volume.
3Ease of operation
If queuing of data transmission and reception is implemented, then data flow control is improved, but processing performance drops due to increased delay
Solution Approach 1:
The patent extracts and eliminates the queuing mechanism from the data transmission system. By implementing direct point-to-point communication without intermediate queues, data flows continuously from sender to receiver, removing queuing delay while maintaining flow control through alternative means such as flow control signals or bandwidth management.
Solution Approach 2:
The patent skips the queuing step entirely in the data transmission process. Data is transmitted directly through the interconnect without being held in buffers or queues, rushing through the communication path as quickly as the physical medium allows, thereby maximizing processing performance.
Data Source
AI summary
A signal processing chip includes a plurality of signal processing blocks each configured to transmit and receive a signal via a signal line, samples the signal on the signal line that is transmitted and received by the signal processing blocks, and transmits, to another signal processing chip, a data frame including information indicating the signal sampled at a timing of satisfying a predetermined condition.