Signal Generation Circuit for Stable Alert Pulse Widths
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Solution Overview
Problem
In semiconductor memory manufacturing, variations in process corners due to differences in transistor parameters across wafers lead to inconsistencies in clock signal cycles, causing pulse widths of alert signals to exceed or fall below specified standards, affecting the reliability of parity check alert systems.
Innovation Solution
A signal generation circuit comprising a clock module, a control module, and a generation module, where the control signal adjusts the pulse width of the target signal by determining the target duration based on the clock signal and process monitor code, ensuring the pulse width remains within a stable range across different process corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed cycle clock signal is used for alert signal generation, then the circuit design is simple, but the pulse width varies beyond specified ranges due to process corner variations
Solution Approach 1:
The patent applies dynamics by making the clock signal cycle adaptive rather than fixed. The clock module dynamically adjusts the cycle of the clock signal based on process monitor codes, allowing the system to adapt to different process corners. This resolves the contradiction by introducing dynamic adjustment mechanisms that maintain pulse width consistency across varying manufacturing conditions without requiring overly complex fixed-cycle control circuits.
Solution Approach 2:
The patent changes the parameter of clock signal cycle based on process monitor codes. By adjusting the clock cycle parameter dynamically according to actual process conditions, the system ensures that alert signal pulse widths remain within specified ranges despite process corner variations. This parameter adaptation approach maintains manufacturing precision while avoiding excessive circuit complexity.
2Manufacturing precision
If the clock signal cycle is adjusted to compensate for process variations, then the pulse width consistency improves, but the device complexity increases
Solution Approach 1:
The patent implements feedback by using process monitor codes to adjust the clock signal cycle. The process monitor codes provide feedback about actual process conditions, and this feedback is used to dynamically adjust the clock cycle to compensate for process corner variations. This feedback mechanism achieves pulse width consistency while keeping the circuit complexity manageable through automated adjustment rather than manual calibration.
Solution Approach 2:
The system performs self-service by automatically adjusting its own clock signal parameters based on process monitor codes. The signal generation circuit monitors its own operating conditions and self-corrects for process variations without requiring external intervention or complex calibration circuits. This self-adjusting capability improves precision while limiting complexity growth.
3Reliability
If process monitor codes are used to adjust clock signal, then compliance with standards is ensured, but the measurement and control difficulty increases
Solution Approach 1:
The patent applies preliminary action by obtaining process monitor codes in advance and using them to pre-adjust the clock signal cycle before alert signal generation. This preliminary adjustment ensures that the system is properly calibrated for the actual process conditions before generating critical alert signals, thereby ensuring standard compliance while simplifying the measurement process through advance preparation.
Data Source
AI summary
A signal generation circuit includes: a clock module, configured to generate a clock signal based on a flag signal; a control module, configured to generate a control signal according to number of transitions of the clock signal within a fixed time; and a generation module, respectively connected to the clock module and the control module, and configured to receive the clock signal, the control signal, and the flag signal, and to generate a target signal. When the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level. After being maintained at the fourth level for a target duration, the target signal changes from the fourth level to the third level. The generation module is further configured to determine the target duration according to the clock signal and the control signal.