Signal Generating Circuit for Full-Cycle Output Synchronization
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Solution Overview
Problem
Existing signal generating circuits struggle to output multiple full-cycle signals within a preset time period, especially when the cycle of the test signal is changed, leading to incomplete cycles.
Innovation Solution
A signal generating circuit comprising a first synchronization circuit, a frequency dividing circuit, a second synchronization circuit, and a synthesis circuit, which synchronizes the beacon signal with a clock signal, performs frequency division to generate a 50% duty cycle signal, and then synchronizes and combines these signals to output full-cycle signals within the preset period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the cycle of the test signal is changed in existing circuit design, then the signal frequency is adjusted, but the requirement to output multiple full-cycle signals within a preset time period cannot be met, resulting in incomplete cycles
Solution Approach 1:
The circuit segments the beacon signal generation into multiple independent stages: a first synchronization circuit aligns the beacon signal with a clock signal, a frequency dividing circuit divides the clock signal to generate a frequency division signal with 50% duty cycle, a second synchronization circuit aligns the first synchronization signal with the frequency division signal, and a synthesis circuit combines them through an AND operation. This segmentation allows each stage to be optimized independently, ensuring complete full-cycle signals while adapting to different signal cycles.
2Productivity
If existing circuit design is used to transmit test signals, then the circuit structure is simple, but it cannot output multiple full-cycle signals within a preset time period when the signal cycle changes
Solution Approach 1:
The circuit merges multiple synchronization and signal generation functions into a unified structure. The first synchronization circuit combines the beacon signal and clock signal, the frequency dividing circuit processes the clock signal, the second synchronization circuit combines the first synchronization signal and frequency division signal, and the synthesis circuit performs the final AND operation. This merging of functions into a coordinated system enables high productivity in generating multiple full-cycle signals while maintaining manageable device complexity through modular design.
Data Source
AI summary
A signal generating circuit and a signal generating method are provided. The signal generating circuit includes a first synchronization circuit configured to synchronize a beacon signal and a first signal edge of a clock signal to generate a first synchronization signal; a frequency dividing circuit configured to receive the clock signal and perform frequency division operation on the clock signal to generate a frequency division signal, wherein the duty cycle of the frequency division signal is 50%; a second synchronization circuit configured to receive the first synchronization signal and the frequency division signal and synchronize the first synchronization signal and a second signal edge of frequency division signal to generate a second synchronization signal; and a synthesis circuit configured to receive the second synchronization signal and the frequency division signal and perform AND operation on the second synchronization signal and the frequency division signal to output full-cycle signals.