Signal Controller Clock Frequency Adjustment for Voltage Ripple Reduction
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Solution Overview
Problem
Display devices experience voltage ripples when the operation load of a signal controller changes from high to low or vice versa, leading to potential damage and display quality deterioration.
Innovation Solution
A display device with a signal controller that generates internal clock signals with varying frequencies during blank periods, allowing for image processing and storage of preset signals, which helps maintain a stable operation voltage and prevent load-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the signal controller operates with varying load (high during image processing, low during blank period), then power consumption is reduced during blank period, but voltage ripple is generated due to load change
Solution Approach 1:
The patent applies preliminary action by having the signal controller perform image processing tasks during the blank period in advance. The controller reads preset image signals from memory and processes them before the actual display period, so that when the display period arrives, the processing workload is already complete, allowing the controller to operate at low load during the actual display without causing voltage ripple.
2Reliability
If the signal controller performs image processing during blank period, then consistent load is maintained and voltage ripple is reduced, but processing time is consumed during blank period
Solution Approach 1:
The patent uses preliminary action to perform image processing during the blank period, which is time when no display output is required anyway. By completing processing tasks during this idle time window, the system maintains consistent load and stabilizes voltage without delaying the actual display output, effectively utilizing otherwise wasted time.
Solution Approach 2:
The patent implements periodic action by alternating between image processing during blank periods and display output during active periods. This periodic pattern allows the controller to cycle through processing and display phases, maintaining consistent operational rhythm and voltage load while ensuring timely display output.
3Productivity
If the clock signal frequency is increased during blank period, then data processing speed is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable rather than fixed. During blank periods, the controller can dynamically increase the clock frequency to boost data processing speed when needed, while during active display periods, the frequency can be reduced to lower power consumption. This dynamic adjustment allows the system to optimize between processing speed and energy efficiency based on operational requirements.
Data Source
AI summary
A display device includes a display panel including: a plurality of pixels; and a signal controller which generates, on a frame-by-frame basis, a display signal based on an input image signal and a control signal from an outside. The signal controller includes a memory which stores a preset image signal, a receiver which receives the control signal, a clock signal modulator which generates an internal clock signal having a first frequency during a blank period, which is determined based on the control signal in a frame period, and a data processor which reads the preset image signal from the memory in response to the internal clock signal for an image processing.