Signal Data Encoding for Low-Power Arithmetic Processing
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Solution Overview
Problem
The existing signal processing methods, particularly in digital communication, face challenges in reducing power consumption due to high bit-wise operation rates when using two's complement representation for data near zero, and the sign magnitude representation's inefficiency in representing subtraction operations, leading to increased circuit scale and power consumption.
Innovation Solution
A signal processing apparatus and method that employs both two's complement and sign magnitude representations, using bit inversion for data conversion without requiring additional addition processing, thereby reducing power consumption and circuit scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two's complement representation is used for data near zero, then addition/subtraction processing is efficient, but bit-wise operation rate increases leading to higher power consumption
Solution Approach 1:
The patent segments the data representation system into two distinct formats: two's complement representation for operation processing and sign magnitude representation for storage processing. This segmentation allows each format to be used in its optimal context, resolving the contradiction between processing efficiency and power consumption.
Solution Approach 2:
The patent dynamically switches between two's complement and sign magnitude representations based on the processing stage. Data is converted to sign magnitude representation before storage to reduce bit-wise operations, then converted back to two's complement for addition/subtraction operations. This dynamic adaptation optimizes both power consumption and processing efficiency.
2Use of energy by moving object
If sign magnitude representation is used for data near zero, then bit-wise operation rate decreases reducing power consumption, but subtraction operations become inefficient and circuit scale increases
Solution Approach 1:
The patent divides the signal processing workflow into distinct segments: storage processing using sign magnitude representation and operation processing using two's complement representation. This segmentation allows sign magnitude to reduce power consumption during storage while two's complement handles subtraction efficiently during operations.
Solution Approach 2:
The patent introduces conversion circuits as intermediary components that translate between sign magnitude and two's complement representations. These conversion circuits enable the system to leverage the advantages of both formats without being constrained by their individual limitations.
3Use of energy by moving object
If data is continuously converted between two's complement and sign magnitude representations, then power consumption is reduced, but conversion processing increases circuit complexity
Solution Approach 1:
The patent applies different representation formats to different parts of the processing system: sign magnitude is used specifically in storage processing parts where bit-wise operations dominate, while two's complement is used in operation processing parts where arithmetic operations are required. This localized application reduces overall system complexity while achieving power savings.
Solution Approach 2:
The patent performs data conversion to sign magnitude representation in advance, before storage operations begin. This preliminary action reduces the frequency of conversions needed during normal operation, thereby reducing circuit complexity while maintaining power consumption benefits.
Data Source
AI summary
A signal processing apparatus comprises an operation processing part that performs operation processing on data represented in the two's complement representation and a storage processing part that performs storage processing on data represented in a second representation format as a data representation format, and in the second representation format, a data value is identical to one in the two's complement representation when the value is positive or zero, and all the bits lower than the most significant bit that indicates the sign in the two's complement representation are inverted when a data value is negative.