Signal Delay Circuit for Adaptive Column Select Pulse Width
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Solution Overview
Problem
Existing memory apparatuses face inefficiencies due to the inability to optimize the pulse width of the delayed column select signal according to process variations, leading to reduced efficiency in data transmission, particularly when P-type transistors in the sense amplifier are stronger than N-type transistors in the data-in drivers.
Innovation Solution
A signal delay circuit is designed with an input inverter, a first inverter, a capacitor, a first transistor, and an output inverter, where the pulse width of the delayed column select signal is varied based on process variations, ensuring optimal pulse width by adjusting the delay time determined by transistor parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple RC delay circuit is used to generate delayed column select signal, then the device complexity is reduced, but the pulse width cannot be optimized according to process variation
Solution Approach 1:
The patent applies dynamics by making the delay time adjustable through a control signal that modifies the effective resistance in the RC delay circuit. The control signal varies the resistance value dynamically, allowing the pulse width to be optimized according to process variations in transistor strength without changing the physical circuit structure.
Solution Approach 2:
The patent changes the resistance parameter in the RC delay circuit by using a control signal to adjust the effective resistance value. This parameter change allows the delay time and pulse width to be optimized for different process conditions, resolving the contradiction between simple circuit structure and adaptability.
2Reliability
If the column select signal pulse width is increased to accommodate stronger P-type transistors, then data transmission reliability is improved, but the writing efficiency deteriorates
Solution Approach 1:
The patent uses dynamic adjustment of the column select signal pulse width based on process variation detection. When P-type transistors are stronger, the pulse width is increased to ensure reliable data transmission. When transistors are weaker, the pulse width is reduced to maintain writing efficiency. This dynamic adaptation resolves the contradiction between reliability and productivity.
Solution Approach 2:
The patent changes the pulse width parameter of the column select signal based on detected process variations. By adjusting this temporal parameter, the system ensures reliable data transmission when needed while maintaining high writing efficiency under normal conditions, thus resolving the contradiction between reliability and productivity.
3Productivity
If the column select signal pulse width is decreased to improve writing efficiency, then productivity is improved, but data transmission reliability deteriorates
Solution Approach 1:
The patent dynamically adjusts the column select signal pulse width based on real-time detection of process variations. When process conditions indicate stronger transistors, the system increases pulse width to ensure reliability. When conditions are normal, it uses shorter pulse widths to maintain high writing efficiency, thus resolving the contradiction between productivity and reliability.
Solution Approach 2:
The patent changes the pulse width parameter dynamically based on process variation detection. This parameter adjustment ensures that data transmission reliability is maintained when transistor strength varies, while preserving high writing efficiency under normal operating conditions, resolving the contradiction between productivity and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures correct data transmission to the sense amplifier by adjusting the pulse width of the delayed column select signal, improving the writing efficiency and data integrity in memory apparatuses by accommodating variations in transistor strengths.
Implementation Method 1
The capacitor C1 is coupled between the output terminal of the inverter IV1 and a ground voltage
Data Source
AI summary
The invention provides a memory apparatus and a signal delay circuit thereof. The signal delay circuit provided by present disclosure includes an input inverter, a first inverter, a capacitor, a first transistor, a second inverter and output inverter. The input inverter receives an input signal and output a signal to the first inverter. The capacitor coupled to an output terminal of the first inverter. The second terminal of the first transistor coupled to the output terminal of the first inverter and the first terminal of the first transistor coupled to an operating voltage. An input terminal of the second inverter is coupled to the output terminal of the first inverter and an output terminal of the second inverter is coupled to the control terminal of the first transistor. The output inverter is used to generate a delayed output signal.