Differential Signal Delay Circuit With Current-Controlled Frequency Tuning
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Solution Overview
Problem
Existing clock and data recovery (CDR) technologies face limitations due to low output frequency and increased parasitic capacitance from varactors, which reduce the maximum achievable frequency and introduce additional wiring-induced capacitive loads.
Innovation Solution
A device with an oscillator ring featuring multiple differential pairs and adjustable quiescent current sources, along with current modulation stages, allows for controllable signal delay and frequency adjustment without increasing parasitic capacitance, using discretized control signals to modulate quiescent currents and achieve frequency variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If varactors are inserted into the oscillator's signal path to achieve frequency variation, then frequency adjustment capability is improved, but parasitic capacitive loads increase and maximum achievable frequency decreases
Solution Approach 1:
The patent extracts the frequency control function from the signal path by using current sources that modulate the oscillation frequency without inserting reactive elements into the signal path. The current sources are connected to the oscillator core in a way that allows frequency control while minimizing parasitic capacitance effects.
Solution Approach 2:
The patent introduces current sources as intermediary elements that control the oscillator frequency indirectly. These current sources act as mediators between the control voltage and the oscillator core, allowing frequency adjustment without direct insertion of varactors into the critical signal path.
2Adaptability or versatility
If multiple varactors are used to achieve frequency variation in both reference and calibration oscillators, then frequency control is improved, but device complexity and parasitic capacitance increase
Solution Approach 1:
The patent implements universal current source circuits that can be used across multiple oscillator stages (reference oscillator, calibration oscillator, and voltage-controlled oscillator). This multi-functional approach reduces the total number of discrete varactor elements needed while maintaining comprehensive frequency control capability.
Solution Approach 2:
The patent merges the frequency control function into integrated current source blocks that serve multiple oscillators simultaneously. By combining control functionality and reducing redundant varactor elements, the overall device complexity is reduced while maintaining the required frequency adjustment capabilities.
3Adaptability or versatility
If additional wiring is added to insert varactors into the signal path, then frequency adjustment is enabled, but parasitic capacitive load increases
Solution Approach 1:
The patent extracts the frequency control function from the main signal path by implementing current modulation stages that control oscillator frequency through current sources rather than through direct varactor insertion. This extraction eliminates the need for additional wiring that would introduce parasitic capacitance into the critical signal path.
Data Source
AI summary
The invention relates to a device (200) for controllably delaying an electrical signal, the device comprising: - a first signal transfer path (207) between a signal input (201) and a signal output (204), the path having -- a first signal transfer stage (208) with a first differential pair (209) and a common, regulatable first quiescent current source (212); - a second signal transfer path (213) between the signal input (201) and the signal output (204), the path having -- a second signal transfer stage (214) with a second differential pair (215) and a common, regulatable second quiescent current source (218), in addition to -- an internal delay stage (219), provided between the signal input (201) and the second signal transfer stage (214) and having a third differential pair (220) and a common, regulatable third quiescent current source (223); and - a signal combination stage (224) for additively superimposing the electrical signal transferred via the first signal transfer path (207) on to the electrical signal transferred via the second signal transfer path (213). In order to prevent or at least reduce parasitic capacitive loads, at least one current modulation stage (235, 236) for regulating the quiescent current of at least one of the first and/or second and/or third quiescent current sources (212, 218, 223) is proposed. Also proposed is a corresponding method for controllably delaying an electrical signal and for delaying the electrical signal using a device of this type.