Programmable Signal Delay for Fast PLL-Independent Frequency Adjustment
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Solution Overview
Problem
Current semiconductor technologies face challenges in managing power dissipation due to increasing DC power leakage and AC power growth, as existing dynamic voltage and frequency scaling methods are limited by the bandwidth of digital phase locked loop devices, requiring faster and more precise frequency adjustments to manage power effectively.
Innovation Solution
A method for fast and smooth frequency adjustment of electronic signals using a signal delay element with a programmable delay line, phase compare and reset logic, adder block, counter block, and decoder block to align pulse edges, allowing immediate frequency changes without altering the reference clock, thereby stabilizing electronic devices in varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a digital phase locked loop device is used to dynamically change frequency, then frequency adjustment capability is provided, but the speed of frequency change is limited by the PLL bandwidth to millisecond region
Solution Approach 1:
The frequency adjustment function is segmented into two independent parts: a frequency generator that produces the base frequency and a signal delay element that adjusts the output frequency by adding variable delays to cycles of the input signal. This segmentation allows the delay element to operate independently from the PLL, enabling sub-nanosecond frequency changes without being constrained by PLL bandwidth limitations.
Solution Approach 2:
A signal delay element is introduced as an intermediary component between the frequency generator and the load. This delay element receives a control signal that specifies the desired output frequency and adjusts the delay applied to each cycle of the input signal accordingly, thereby mediating the frequency transformation in a manner independent of PLL bandwidth constraints.
2Productivity
If frequency is changed rapidly to manage power dissipation, then power management efficiency is improved, but dI/dt slew rate problems occur
Solution Approach 1:
The signal delay element dynamically adjusts the delay applied to each cycle of the input signal based on the desired output frequency. By continuously varying the delay in real-time, the system can achieve rapid frequency transitions while controlling the rate of change of current, thereby preventing dI/dt slew rate problems even during fast frequency changes.
Solution Approach 2:
The system changes the delay parameter of the signal delay element to achieve frequency adjustment. By modifying the delay value in response to control signals, the output frequency can be rapidly adjusted across a wide range (5% to 50%) without causing harmful dI/dt slew rate effects, as the delay changes are smoothly applied to each signal cycle.
3Loss of energy
If DVS is used for power savings with application-specified measures to estimate CPU requirements, then power consumption is reduced, but frequency adjustment speed is limited to millisecond region
Solution Approach 1:
The signal delay element is pre-configured with the capability to adjust delays for each cycle of the input signal. When a frequency change is required, the delay element can immediately apply the appropriate delay without waiting for PLL settling time, enabling sub-nanosecond frequency transitions that support rapid DVS responses to changing CPU workload requirements.
Data Source
AI summary
The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.