On-Chip Signal Delay Measurement Circuit Using Shift Registers
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Solution Overview
Problem
Current methods for measuring signal propagation delays in integrated circuits (ICs) are limited by the need for adjustable delay lines and off-chip measuring equipment, which increase costs and complexity, and struggle to accurately measure delays in ICs with hundreds or thousands of paths simultaneously.
Innovation Solution
A circuit using a shift register and asynchronous clocks to measure signal delays between edges, allowing for simultaneous measurement of multiple paths without adjustable delay lines or off-chip equipment, by applying an alternating signal and counting clock cycles between detected edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If adjustable delay lines and off-chip measuring equipment are used to measure signal propagation delays, then measurement accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The invention extracts the delay measurement function from external measuring equipment and implements it using on-chip boundary scan circuitry. The TAP controller and boundary scan register, already present for test access, are repurposed to perform delay measurements by capturing signal edges and counting clock cycles, eliminating the need for external adjustable delay lines and complex off-chip measurement equipment.
Solution Approach 2:
The boundary scan circuitry performs self-measurement of signal propagation delays using its own internal resources. The TAP controller generates test patterns, the boundary scan register captures output edges, and the circuit counts clock cycles to determine delay, allowing the IC to measure its own delays without external assistance.
2Adaptability or versatility
If adjustable delay lines are used to measure delays in multiple paths simultaneously, then measurement coverage is improved, but measurement time increases
Solution Approach 1:
The invention uses periodic clock signals to systematically measure delays across multiple paths. The TAP controller sequentially applies test patterns to different paths, and the boundary scan register captures edges at regular clock intervals, enabling efficient measurement of multiple paths through periodic sampling rather than requiring adjustable delays for each path.
Solution Approach 2:
The boundary scan register is pre-configured to capture output edges at specific clock cycles. By predeterminedly setting up the capture logic and clock timing, the circuit can immediately begin measurements when test patterns are applied, reducing setup time and enabling rapid sequential measurement of multiple paths.
3Adaptability or versatility
If on-chip adjustable delay circuits are used to control launch and capture times, then delay measurement flexibility is improved, but jitter and delay variation increase due to power supply noise and temperature variations
Solution Approach 1:
Instead of using on-chip adjustable delay circuits that are susceptible to jitter and variation, the invention uses a stable external clock signal as a reference. The clock cycles are counted to measure delays, and the same clock is used for both launching and capturing, creating a consistent timing reference that is immune to power supply noise and temperature variations affecting on-chip delay elements.
Data Source
AI summary
Various aspects of the present invention relate to techniques of measuring delays between edges of signals of a circuit. Alternating signals, synchronous to a first clock, are supplied to a plurality of nodes of the circuit. First samples of a plurality of signals associated with the alternating signals are captured using a first capture clock, of which sampling instants are synchronous to a second clock. Second samples of the first samples are then captured using a second capture clock, of which sampling instants are also synchronous to the second clock. The captured second samples are conveyed via a shift register to a plurality of modulo counters. The measured signal delay includes a timing skew associated with the first clock and a timing skew of the first capture clock but not a timing skew of the second capture clock.