Signal Domain Conversion Hardware for Real-Time FFT Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing signal processing systems face challenges in efficiently converting signals between time and frequency domains in real-time, as they often require large amounts of fast memory, which is expensive and limited, and internal FFT hardware blocks are inadequate for continuous real-time conversions.
Innovation Solution
The system employs remote medium-speed memory and domain conversion hardware, such as OLA/STFFT and OLA/iSTFFT hardware, to perform signal conversions without relying on internal fast memory or FFT hardware blocks, allowing for real-time processing by offloading memory-intensive tasks to separate hardware components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If internal fast memory and FFT hardware blocks are used for signal conversion, then conversion speed is improved, but memory cost and device complexity increase
Solution Approach 1:
The patent extracts the FFT computation function from the main processor and implements it as a separate hardware acceleration module. This module is specifically designed to perform FFT operations independently, removing the burden from the main processor while maintaining high conversion speed.
Solution Approach 2:
The patent introduces an intermediate buffer memory structure that mediates between the input signal source and the FFT processing module. This buffer manages data flow and timing, enabling efficient real-time processing without requiring excessive fast memory resources in the main processor.
2Productivity
If large amounts of fast memory are allocated for signal processing, then processing capability is improved, but memory cost increases
Solution Approach 1:
The patent segments the memory system into multiple levels: fast memory for critical real-time operations, medium-speed memory for buffer storage, and slow memory for data storage. This segmentation allows each memory type to be optimized for its specific function, reducing the total amount of expensive fast memory required.
Solution Approach 2:
The patent changes the speed parameter of memory by using different types of memory for different purposes. Instead of using uniformly fast memory throughout the system, it employs a hierarchy of memory speeds matched to the timing requirements of different processing stages.
3Productivity
If internal FFT hardware blocks are used, then conversion efficiency is improved, but they are inadequate for continuous real-time conversions
Solution Approach 1:
The patent prepares data in advance by storing incoming signals in buffer memory at medium speed before they are processed by the FFT module. This preliminary buffering ensures that data is ready for immediate processing when the FFT module becomes available, maintaining continuous real-time operation.
Solution Approach 2:
The patent designs an overlapping processing architecture where data buffering, FFT computation, and result processing occur simultaneously in different stages. This ensures that the useful action of signal conversion continues without interruption, achieving reliable continuous real-time processing.
Data Source
AI summary
A device for processing a signal includes a processing module used to process data in a domain. The device includes domain conversion hardware and memory, both separate from the processing module. The memory receives and sends data represented in a first domain to the domain conversion hardware. The domain conversion hardware converts the first domain data into the second domain data that may be used or processed by the processing module. The second domain data is then accessed and used by the processing module for processing.