Hardware Simulation Signal Dumping via Dynamic Partial Aliasing

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Solution Overview

Problem

Current HDL simulators face inefficiencies in signal dumping during simulation, leading to increased runtime overhead and storage usage due to the dumping of signals with similar waveforms, which are not effectively reduced by existing static aliasing techniques.

Innovation Solution

Dynamic partial aliasing of signals with similar waveforms, where a master signal is identified and only its waveform is dumped, with slave signals being aliased and temporarily not dumped, reducing the number of signals to be stored and processed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all signals are dumped during simulation, then complete debugging information is obtained, but runtime overhead and storage usage increase significantly

Engineering Contradiction:
Improvedebugging information completenessVSAvoidsimulation runtime overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges signals with similar waveforms by identifying master signals and aliasing slave signals to them. When waveforms are similar, multiple slave signals are combined into a single master signal representation, reducing the total number of signals that need to be dumped and processed, thereby decreasing runtime overhead while maintaining debugging effectiveness

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic aliasing where the aliasing relationship between signals is not fixed but changes during simulation based on waveform similarity. The system continuously monitors waveform characteristics and dynamically adjusts which signals are aliased together, allowing the debugging information to adapt to changing signal behaviors during simulation

Inventive Principle:
Principle #15Dynamics

2Reliability

If all signals are dumped during simulation, then complete debugging information is obtained, but disk usage increases significantly

Engineering Contradiction:
Improvedebugging information completenessVSAvoidstorage space usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

By merging slave signals with their master signals when waveforms are similar, the patent reduces the total quantity of signal data that needs to be stored. Instead of dumping multiple redundant signals, only the master signal is dumped, significantly reducing disk usage while preserving essential debugging information

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent discards redundant signal data by not dumping slave signals that are aliased to master signals. The information is recovered on-demand through the aliasing relationship, allowing the system to eliminate unnecessary storage while maintaining the ability to retrieve signal information when needed for debugging

Inventive Principle:
Principle #34Discarding and recovering

3Loss of time

If static aliasing is applied to reduce signal dumping, then storage and runtime are improved, but signals with similar waveforms are not effectively reduced

Engineering Contradiction:
Improvesimulation runtimeVSAvoidsignal reduction accuracy
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent transitions from static aliasing to dynamic aliasing by continuously monitoring waveform similarity during simulation. This allows the system to accurately identify and alias signals that have similar waveforms at any given time, improving signal reduction accuracy compared to static methods that use fixed aliasing rules

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements feedback by continuously comparing waveform characteristics of signals during simulation. This feedback mechanism allows the patent to dynamically adjust aliasing decisions based on actual signal behavior, ensuring that only signals with truly similar waveforms are aliased together, thereby improving reduction accuracy

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11275877B2Hardware simulation systems and methods for reducing signal dumping time and size by fast dynamical partial aliasing of signals having similar waveform
Publication Date: 2022.03.15 SYNOPSYS INC
  • US11275877B2 patent drawing
  • US11275877B2 patent drawing
  • US11275877B2 patent drawing

AI summary

Hardware simulation systems and methods for reducing signal dumping time and size of by fast dynamical partial aliasing of signals having similar waveform are provided. One example system is configured to receive, in real-time, a first signal from a producer entity; determine a first signal signature associated with the first signal; determine, in real-time, a second signal signature associated with the second signal; upon determining that the first signal signature matches the second signal signature, designate the first signal as a master signal and designate the second signal as a slave signal; and stop dumping the second signal to a storage space.