Signal Envelope Detector With Capacitive Divider for Overload Sensing
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Solution Overview
Problem
Electronic circuits, such as on-chip buffers of high-speed Analog-Digital Converters (ADCs), are vulnerable to input overload situations that can cause irreversible damage due to overstress beyond the Safe-Operating-Area (SOA), necessitating effective signal monitoring and detection solutions.
Innovation Solution
A signal envelope detector is designed with a capacitive voltage divider and a source follower transistor to extend the input detection range while preventing potential breakdown, coupled with a rectifier circuit and low-pass filter for real-time envelope tracking, and an overload detector using a reference generation circuit and comparator to detect overloads in differential signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the input detection range is extended to monitor higher power signals, then the ability to detect overload conditions is improved, but the risk of circuit breakdown and damage increases
Solution Approach 1:
A capacitive voltage divider is introduced as an intermediary element between the input signal source and the detection circuit. This divider attenuates the input signal by a controlled amount (e.g., 6 dB), allowing the detection circuit to safely monitor higher power signals without being directly exposed to potentially damaging voltage levels. The capacitive nature of the divider also provides frequency-dependent behavior that maintains effectiveness across a wide bandwidth.
2Speed
If real-time envelope tracking is implemented to provide immediate overload detection, then the response time to overload conditions is improved, but the circuit complexity increases
Solution Approach 1:
The patent replaces complex active envelope detection circuits with a passive capacitive voltage divider followed by a simple rectifier and low-pass filter stage. This substitution eliminates the need for complex active components and control logic while achieving real-time envelope tracking. The passive nature of the capacitive divider ensures automatic operation without power consumption or complex biasing requirements.
3Reliability
If a capacitive voltage divider is used to attenuate input signals for safe monitoring, then the protection against overload damage is improved, but the detection precision at low signal levels may deteriorate
Solution Approach 1:
The patent employs a capacitive voltage divider whose attenuation characteristic changes with frequency. At low frequencies, the capacitive reactance is high providing greater attenuation and protection. At high frequencies, the capacitive reactance decreases reducing the attenuation effect. This parameter change with frequency ensures that the fixed threshold detector maintains appropriate sensitivity across a wide frequency range without requiring adjustable components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables real-time monitoring and detection of input overloads, protecting circuits from damage by adjusting attenuation levels and providing a wide frequency and power detection range with minimal power consumption and silicon area, ensuring increased product reliability.
Implementation Method 1
a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal
Implementation Method 2
a rectifier circuit coupled to the source follower transistor and configured to receive and rectify an output signal of the source follower transistor
Implementation Method 3
a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit
Data Source
AI summary
A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor. In addition, the signal envelope detector includes a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit.