Signal-Gated Digital Delay Line for Low-Power Phase Selection
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Solution Overview
Problem
Digital controlled delay lines (DCDLs) in integrated circuits consume excessive power due to the need for numerous delay cells to achieve fine granularity in delay time adjustments, leading to high operation power consumption.
Innovation Solution
The implementation of a signal gated delay line and phase selector with logic gates, where unused signal gated delay cells and logic gates are prevented from propagating signals, reducing power consumption by setting them to constant values and optimizing the number of logic gates in the phase selector based on the number of delay cells, specifically using log2 p logic gates for p being a power of 2 and (integer part of log2 p)+1 for p not being a power of 2.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a huge amount of delay cells are used to achieve finer granularity in delay time adjustments, then delay precision is improved, but power consumption increases
Solution Approach 1:
The delay line is segmented into multiple delay cells, each contributing a specific delay amount. By selectively enabling or disabling individual delay cells through control signals, the total delay can be precisely adjusted in fine granularity steps without requiring all cells to be active simultaneously, thus reducing overall power consumption while maintaining delay precision.
Solution Approach 2:
The delay line employs dynamic control mechanisms where the activation state of each delay cell can be changed in real-time based on control signals. This dynamic switching allows the system to achieve fine delay adjustment by activating only the necessary number of delay cells for the required delay period, rather than keeping all cells continuously active, thereby reducing power consumption while preserving delay precision.
2Adaptability or versatility
If more delay cells are added to increase delay range, then delay flexibility is improved, but device complexity increases
Solution Approach 1:
The delay line is divided into multiple discrete delay cells, each providing a specific delay increment. This segmentation allows the system to achieve a wide delay range by selectively combining different numbers of delay cells, providing flexible delay adjustment without requiring a single complex delay element. The modular structure maintains manageable complexity while expanding the delay range.
Solution Approach 2:
The system uses dynamic control signals to selectively enable or disable individual delay cells based on the required delay period. This dynamic configuration allows the delay line to adapt to different delay requirements flexibly, achieving a wide range of delay values without permanently configuring all possible delay paths, thus managing device complexity while maximizing delay flexibility.
Data Source
AI summary
A digital controlled delay line (DCDL) includes a signal gated delay line generating a delayed signal, a phase selector, a controller, an input signal and an output signal. The phase selector includes logic gates to couple the delayed signal from the signal gated delay line to the output signal. Preventing signal propagation to unused cells and logic gates reduces power consumption. The number of logic gates in the phase selector the delayed signal passes through is log2 p, wherein p is the number of the signal gated delay cells in the signal gated delay line and p is a power of 2. The number of logic gates is (integer part of log2 p)+1, wherein p is the number of the signal gated delay cells and p is not a power of 2.