Signal Loop Busbar Layout for Matched Low-Inductance Power Modules
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Solution Overview
Problem
Current power modules face challenges with inductance issues in signal loop busbars, which affect the operation and efficiency of power semiconductor devices, particularly due to asymmetrical pinouts and high inductance values, leading to inefficiencies in signal propagation and device switching.
Innovation Solution
The implementation of matched and low inductance signal loop busbars in semiconductor power modules, achieved through optimized configurations and arrangements of high side and low side Kelvin and gate busbars, including uniform gaps and plane alignments, to reduce inductance and ensure equivalent inductance values for both signal loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional busbar arrangements are used, then manufacturing is simpler, but signal loop inductance is high which deteriorates device operation
Solution Approach 1:
The busbar configuration uses asymmetrical routing where the high-side and low-side signal loops are deliberately designed with different geometric paths but equivalent inductance values. This asymmetrical arrangement allows optimization of each loop's inductance to match, resolving the contradiction between simple manufacturing and low inductance operation.
Solution Approach 2:
The patent adjusts geometric parameters of the busbars including trace widths, spacing distances, and path lengths to achieve equivalent inductance values. By changing these physical parameters, the signal loop inductances are optimized to be matched while maintaining manufacturability through standard PCB fabrication processes.
2Speed
If inductance is reduced through optimized busbar arrangement, then signal propagation improves, but manufacturing precision requirements increase
Solution Approach 1:
The design achieves equipotentiality in terms of inductance matching, where both high-side and low-side signal loops are designed to have equivalent inductance values. This balanced approach reduces signal propagation issues while the use of standard PCB trace geometries keeps manufacturing precision requirements within conventional tolerances.
3Reliability
If matched inductance is achieved for both signal loops, then device switching performance improves, but busbar design complexity increases
Solution Approach 1:
The busbar design uses universal PCB trace routing patterns that can be applied to both high-side and low-side signal loops. By using the same design methodology and geometric principles for both loops, the patent achieves matched inductance while avoiding excessive design complexity through pattern reuse and standardization.
Data Source
AI summary
A power module having a plurality of bus bars. The power module and/or bus bars being configured with features to reduce inductance; and/or the power module and/or bus bars are configured with features to have a substantially equivalent inductance.