Pulse-Controlled Signal Output Circuit for Adjustable Edge Delay
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Solution Overview
Problem
Existing semiconductor circuits face challenges in generating stagger signals that are equally spaced, where synchronous signals result in poor controllability of delay and increased circuit area and power consumption, while asynchronous signals require additional delay units, also increasing circuit size and power consumption.
Innovation Solution
A signal output circuit that generates a delayed signal with controllable delay using a first and second pulse signal, comprising a first control module, a second control module, and a signal output module, which includes a first receiving unit, a second receiving unit, and a latch unit, to adjust the rising and falling edges of the output signal without requiring additional delay units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If synchronous signals are used to generate stagger signals, then the delay between signals is fixed as an integer multiple of clock period, but the controllability of delay is poor
Solution Approach 1:
The patent changes the control parameter from synchronous clock cycles to asynchronous pulse widths. By varying the pulse width parameter of the input pulse signal, the delay time can be continuously adjusted without being constrained to integer multiples of a clock period, thereby improving delay controllability while maintaining a relatively simple circuit structure.
Solution Approach 2:
The patent transitions from a static delay system (fixed delay based on clock cycles) to a dynamic delay system where the delay time can be adjusted by changing the pulse width of the input signal. This dynamic approach allows the delay to adapt to different requirements without restructuring the circuit.
2Ease of operation
If asynchronous signals with delay units are inserted to generate stagger signals, then the delay between signals is well controllable, but the area of circuit layout and power consumption are significantly increased
Solution Approach 1:
The patent merges the delay function with the signal generation function. Instead of using separate delay units in addition to the signal generation circuit, the delay is achieved by directly controlling the pulse width of the input signal, which is then processed by the existing signal generation circuitry. This integration eliminates the need for additional delay units, reducing circuit area.
Solution Approach 2:
The input pulse signal itself serves the dual purpose of triggering the signal generation and providing the delay control. The pulse width of the input signal directly determines the delay time, eliminating the need for external delay units. The circuit uses the input signal's own characteristics to achieve the delay function.
3Ease of operation
If asynchronous signals with delay units are inserted to generate stagger signals, then the delay between signals is well controllable, but the power consumption of circuit is significantly increased
Solution Approach 1:
The patent merges the delay function with the signal generation function. Instead of using separate delay units in addition to the signal generation circuit, the delay is achieved by directly controlling the pulse width of the input signal, which is then processed by the existing signal generation circuitry. This integration eliminates the need for additional delay units, reducing circuit area.
Solution Approach 2:
The input pulse signal itself serves the dual purpose of triggering the signal generation and providing the delay control. The pulse width of the input signal directly determines the delay time, eliminating the need for external delay units. The circuit uses the input signal's own characteristics to achieve the delay function.
Data Source
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AI summary
Embodiments of the disclosure provide a signal output circuit and a circuit for outputting a delayed signal. The signal output circuit includes: a first control module, a second control module and a signal output module. The first control module is configured to receive a first pulse signal and an input signal, and output a first adjustment signal, a first preset edge of the first adjustment signal has a first delay relative to a rising edge of the input signal, the first delay being a pulse period of the first pulse signal. The second control module is configured to receive a second pulse signal and the input signal, and output a second adjustment signal, where a second preset edge of the second adjustment signal has a second delay relative to a falling edge of the input signal, the second delay being a pulse period of the second pulse signal. And the signal output module is configured to receive the first adjustment signal and the second adjustment signal, and output a delayed output signal, a rising edge of the delayed output signal is generated according to the first preset edge of the first adjustment signal, and a falling edge of the delayed output signal is generated according to the second preset edge of the second adjustment signal. Therefore, according to the embodiments of the disclosure, a delayed signal with a controllable delay can be generated, and the area of the circuit layout will be smaller, and the power consumption of the circuit will be lower.