Signal Receiving Circuit With Discrete Phase Delay Control
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Solution Overview
Problem
In DDR memory interfaces, signal receiving circuits face challenges in maintaining optimal timing relationships between internal clock signals and received data signals due to delay variations, which can impair data transmission reliability and processing speed.
Innovation Solution
A signal receiving circuit with a phase detection unit and a delay control unit that detects phase differences between received signals and clock signals, adjusting the phase of the received signal within a predetermined range to synchronize with the clock signal, using phase differences as units for delay adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the phase of the received signal is adjusted using continuous delay control, then the timing relationship between clock signal and data signal is optimized, but the circuit complexity increases
Solution Approach 1:
The delay control is segmented into discrete steps based on predetermined phase differences. Instead of continuous adjustment, the phase detection unit detects phase differences and the delay control unit adjusts the received signal phase in discrete increments corresponding to these predetermined phase differences, simplifying the circuit while maintaining timing precision.
Solution Approach 2:
The invention changes the delay amount parameter in discrete steps rather than continuously. The delay control unit changes the delay amount of the received signal by using the predetermined phase difference as a unit, transforming the continuous parameter into discrete levels, which reduces circuit complexity while preserving essential timing control.
2Adaptability or versatility
If the delay amount is increased to cover larger phase variations, then the adaptability improves, but the processing speed decreases
Solution Approach 1:
The system dynamically adapts to different phase variation scenarios by detecting the actual phase difference and applying appropriate discrete delay adjustments. The delay control unit responds to detected phase differences by changing the delay amount in predetermined units, providing adaptive coverage without excessive processing overhead.
Solution Approach 2:
The invention uses partial action by adjusting the delay amount in discrete steps rather than applying maximum delay continuously. This allows the system to achieve sufficient phase alignment with minimal processing, improving speed while maintaining adaptability through selective application of delay units.
Data Source
AI summary
A signal receiving circuit includes a phase detection unit and a delay control unit. The phase detection unit detects a phase difference between a received signal and a clock signal. The delay control unit receives the phase difference, delays a phase of the received signal in a range not exceeding a delay amount determined by using a predetermined phase difference as a unit, and changes, when the phase difference exceeds the predetermined phase difference, a delay amount of the received signal by using the predetermined phase difference as a unit.