Signal Pre-routing in Hierarchical IC Design
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Solution Overview
Problem
Current integrated circuit design methodologies require manual entry of complex non-functional-intent structures, such as pervasive logic and clock control structures, which leads to increased design burden, human error, and degraded simulation performance due to the need for explicit expression of all design elements in HDL files.
Innovation Solution
A design methodology that supports multiple levels of abstraction, allowing for the pre-routing of signals and insertion of technology-specific structures in a hierarchical integrated circuit design, reducing the need for manual entry of non-functional-intent code and improving simulation performance by separating functional and non-functional design elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual entry of non-functional-intent structures is required, then complete design specification is achieved, but design burden and error rate increase
Solution Approach 1:
The system performs automated pre-routing of signals and insertion of technology-specific structures without requiring manual intervention. The processor automatically processes entity instances in bottom-up manner, inserting scan chains, clock control structures, and other pervasive logic based on design hierarchy, thereby eliminating manual entry errors while maintaining complete design specification
Solution Approach 2:
The system performs pre-routing of signals before final design compilation. By anticipating and pre-establishing signal paths through multiple hierarchy levels and pre-inserting technology-specific structures, the system eliminates the need for manual entry during later design stages, reducing both effort and error rate
2Reliability
If all design elements are explicitly expressed in HDL files, then complete design model is created, but simulation performance degrades
Solution Approach 1:
The design model is segmented into functional-intent portions and non-functional-intent portions. The processor selectively processes only functional-intent code during simulation while automatically generating and inserting non-functional-intent structures (scan chains, DFT logic, clock control) as needed, thereby maintaining design completeness while improving simulation performance by excluding unnecessary logic from simulation models
3Manufacturing precision
If technology-specific structures are manually entered, then design specificity is achieved, but adaptability to technology changes decreases
Solution Approach 1:
The system dynamically adapts technology-specific structures based on the target technology generation. The processor automatically selects and inserts appropriate scan chain configurations, clock control structures, and other pervasive logic based on technology parameters, allowing the design to adapt to different technology nodes without manual modification of HDL code
Data Source
AI summary
Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated circuit design, a signal through one or more levels of design hierarchy between a signal source at a higher level of the design hierarchy and an entity instance at a lower level of the design hierarchy. The processor processes entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design. During the processing, the processor inserts into a particular entity instance of the design hierarchy a technology-specific structure and connects the technology-specific structure to the signal pre-routed to the particular entity instance by the pre-routing.