Signal Processing Circuit Address Conversion for SDRAM Capacity
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Solution Overview
Problem
Conventional signal processing circuits are unable to fully utilize the storage capacity of SDRAMs with increased capacity, such as 512 Mbits, due to limitations in address data generation, leading to increased development costs when upgrading to support larger memory capacities.
Innovation Solution
A signal processing circuit with an address conversion section that adjusts address data bits, allowing it to access SDRAMs with different capacities by generating appropriate row and column address data, reducing the load on circuit design and development costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the SDRAM storage capacity is increased to support higher quality signal processing, then the data storage capability is improved, but the address generation circuit complexity increases and development costs rise
Solution Approach 1:
The address generation section is designed to generate both 13-bit row address data and 14-bit row address data using the same circuit structure. This universal address generation capability allows the system to support both 256 Mbit SDRAM (requiring 13-bit addresses) and 512 Mbit SDRAM (requiring 14-bit addresses) without requiring separate address generation circuits for each memory capacity, thereby reducing circuit complexity and development costs.
Solution Approach 2:
The system adapts to different SDRAM capacities by changing the parameter of row address data bit length. The address generation section can output either 13-bit or 14-bit row address data depending on the connected SDRAM capacity, allowing the same circuit to work with different memory sizes by simply adjusting the address width parameter rather than redesigning the entire address generation circuit.
2Adaptability or versatility
If a new address generation section is designed to support 512 Mbit SDRAM, then the compatibility with larger memory is improved, but the development cost increases
Solution Approach 1:
The address generation section is designed with universal functionality to support multiple SDRAM capacities (both 256 Mbit and 512 Mbit) using a single circuit design. This eliminates the need to develop separate address generation sections for different memory capacities, significantly reducing development costs while maintaining full compatibility with various SDRAM sizes.
Solution Approach 2:
The address generation section dynamically adapts its output based on the connected SDRAM capacity. The circuit can adjust its address generation behavior (13-bit or 14-bit row addresses) according to the memory capacity detected or configured, providing flexibility and compatibility across different memory sizes without requiring multiple fixed designs.
3Quantity of substance
If the SDRAM capacity is increased from 256 Mbits to 512 Mbits, then the data storage capability is improved, but the address data bit length changes requiring circuit redesign
Solution Approach 1:
The system handles the transition from 256 Mbit to 512 Mbit SDRAM by changing the parameter of row address bit length from 13 bits to 14 bits. The same address generation circuit performs this parameter adjustment without structural redesign, accommodating the increased storage capacity requirement while maintaining circuit simplicity.
Solution Approach 2:
The address generation section serves multiple functions by generating both 13-bit and 14-bit row address data from the same circuit. This multi-functionality allows seamless support for different SDRAM capacities (256 Mbit and 512 Mbit) without requiring separate dedicated circuits for each capacity level.
Data Source
AI summary
A signal processing circuit includes a signal processing section which generates first address data and second address data in accordance with data processing, reads data stored in an external memory based on the first address data and the second address data for performing a predetermined processing, and outputs processed data along with the first address data and the second address data, an address conversion section which, receiving the first address data and the second address data input thereto, holds at least 1 bit of the first address and outputs third address data, and also adds the at least 1 bit of the held first address data to the second address and outputs fourth address data, and a data interface which performs a writing operation or a reading operation of the data processed by the signal processing section with respect to the external memory on the basis of a time when the address conversion section outputs the third address data and the forth address data.