Signal Processing Board Noise Reduction via Six-Layer Substrate
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Solution Overview
Problem
The demand for smaller and higher density signal processing boards in image forming apparatuses, such as printers and copiers, necessitates the use of multilayer substrates with increasing numbers of layers, posing challenges in downsizing and noise reduction.
Innovation Solution
A signal processing board utilizing a six-layer substrate with specific arrangements of semiconductor elements, signal transmission planes, ground planes, power supply planes, and bypass capacitors, which are electrically connected in a manner that optimizes space usage and minimizes noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers of the multilayer substrate is increased to achieve smaller and higher density signal processing boards, then the integration density is improved, but the noise level increases due to high-frequency signal transmission
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional multilayer stacking, utilizing vertical space to increase integration density while managing noise through strategic layer assignment and grounding schemes across multiple dimensions
Solution Approach 2:
Ground planes and bypass capacitors are introduced as intermediary elements between signal transmission paths and power supply networks, serving as noise filtering mediators that prevent high-frequency noise from coupling between different signal paths
2Object-affected harmful factors
If bypass capacitors are added to reduce noise by securing return current paths, then the noise reduction is improved, but the device complexity increases
Solution Approach 1:
Multiple ground planes and bypass capacitors are merged into an integrated noise management system where capacitors are strategically placed at semiconductor element mounting positions, combining grounding functions across different layers to reduce noise without proportionally increasing complexity
Solution Approach 2:
Bypass capacitors are placed locally at specific positions where semiconductor elements are mounted, providing targeted noise reduction at critical interfaces rather than uniform noise management across the entire board, thus reducing overall complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration achieves downsizing of the signal processing board while reducing noise, especially when transmitting high-frequency signals, by effectively managing power supply and ground planes and utilizing bypass capacitors to secure return current paths.
Implementation Method 1
a bypass capacitor arranged on an outer surface of the first layer or the sixth layer and electrically connected to the first power supply plane and the second ground plane
Implementation Method 2
utilizing bypass capacitors to secure return current paths
Data Source
AI summary
A signal processing board includes a six-layer substrate. A plurality of signal transmission planes are formed in a first layer, a third layer, a fourth layer, and a sixth layer. A first ground plane is formed in a second layer. A first power supply plane is formed in a fifth layer and electrically connected to the first semiconductor element. A second power supply plane is formed in the fifth layer and electrically connected to the second semiconductor element. A second ground plane is formed in the fifth layer. A first bypass capacitor is electrically connected to the first power supply plane and the second ground plane. A second bypass capacitor is electrically connected to the second power supply plane and the second ground plane.