Signal Processing Circuit for DRAM Command Address Sampling
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) systems face challenges in efficiently processing and controlling command address signals under a parity clock, requiring effective signal processing circuits to accurately represent binary bits as 1 or 0.
Innovation Solution
A signal processing circuit comprising a first signal latch circuit driven by an even clock and a second signal latch circuit driven by an odd clock, both aligned with a reference clock, along with a decoder to output control signals, ensuring correct sampling and decoding of command address signals under a parity clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock signal is used to drive the signal latch circuit, then the circuit structure is simple, but clock overlapping glitches occur and signal sampling accuracy deteriorates
Solution Approach 1:
The patent divides the single clock signal into two separate clock signals (even clock and odd clock) that are non-overlapping in time. The even clock drives the first signal latch circuit to sample even-numbered bits, while the odd clock drives the second signal latch circuit to sample odd-numbered bits. This segmentation eliminates clock overlapping glitches and improves signal sampling accuracy while maintaining relatively simple circuit structure.
2Productivity
If the clock frequency is increased to improve processing speed, then productivity increases, but clock overlapping glitches worsen and signal integrity deteriorates
Solution Approach 1:
The patent employs periodic alternating action by using two clock signals with different phases (even clock and odd clock). These clocks operate in a periodic manner where one is active while the other is inactive, eliminating overlapping glitches. This periodic action allows higher processing speeds to be achieved without compromising signal integrity, as each latch circuit is driven by a clean, non-overlapping clock signal.
3Device complexity
If a single latch circuit is used, then the device complexity is low, but the ability to correctly decode command address signals under parity clock deteriorates
Solution Approach 1:
The patent segments the command address signal processing into two parallel paths: one for even-numbered bits and one for odd-numbered bits. The first signal latch circuit processes even bits under the even clock, while the second signal latch circuit processes odd bits under the odd clock. This segmentation enables correct decoding of command address signals under parity clock while keeping the overall device complexity manageable through modular design.
Data Source
AI summary
A signal processing circuit includes a first signal latch circuit, a second signal latch circuit, and a decoder. The first signal latch circuit receives a command address signal and is driven by an even clock; the second signal latch circuit receives the command address signal and is driven by an odd clock; and the decoder is connected to the first signal latch circuit and the second signal latch circuit, and outputs a control signal. Both the even clock and the odd clock have a frequency equal to that of a reference clock, and both the even clock and the odd clock have a rising edge aligned with a rising edge of the reference clock.