Signal Processing Circuit Clock Selection for Image Apparatus
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Solution Overview
Problem
Existing image processing apparatuses face design and cost burdens due to the need for different clock frequencies and supply patterns for various models, leading to inefficiencies in signal processing circuits that transfer signals between external and internal devices.
Innovation Solution
A signal processing circuit with a clock selecting unit, data latch units, and a data retaining unit that can operate with multiple clock patterns, allowing it to select and output appropriate clocks and data according to the selected clock, ensuring compatibility with various clock supply patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different clock frequencies and supply patterns are used for various product models, then each model can be optimized for its specific function, but the design burden increases and cost increases
Solution Approach 1:
The signal processing circuit is designed with a clock selecting unit that can accept multiple different clock signals from different systems and select the appropriate one. This allows a single circuit design to support various clock patterns (including SSC, PLL, and different clock supply directions) that were previously required separate dedicated designs, thereby reducing design burden while maintaining adaptability across product models
2Adaptability or versatility
If different clock frequencies and supply patterns are used for various product models, then each model can be optimized for its specific function, but the cost of the apparatus increases
Solution Approach 1:
By designing a universal signal processing circuit with clock selection capability, the need for multiple model-specific circuit versions is eliminated. This single standardized design can be manufactured across all product models, reducing manufacturing complexity and cost while supporting different clock patterns through software or configuration-based clock selection
3Device complexity
If a fixed clock pattern is used in the signal processing circuit, then the circuit design is simplified, but the circuit cannot be compatible with various clock supply patterns
Solution Approach 1:
The signal processing circuit incorporates a clock selecting unit that dynamically chooses between multiple clock signals based on the operational mode or configuration. This dynamic clock selection allows the circuit to adapt to different clock supply patterns (external clock, internal clock, SSC, PLL) without requiring multiple fixed designs, thereby maintaining relative design simplicity while achieving broad compatibility
Data Source
AI summary
A signal processing circuit transfers a signal between an externally connected device and an internal circuit. The signal processing circuit includes a clock selector that selects and outputs any one of clocks received from plural systems; data latch units that respectively latch, according to the respective clocks received from the systems, data pieces being input; a data selector that selects and outputs, among the data pieces latched, a data piece latched according to the selected clock; and a data retaining unit that temporarily retains the data between the data latch units and the internal circuit. When the data is processed between the data retaining unit and the internal circuit, the data retaining unit operates according to an operating clock of the internal circuit, but when the data is processed between the data retaining unit and the data latch units, the data retaining unit operates according to the selected clock.