Signal Processing Device Double Buffer Latency Reduction
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Solution Overview
Problem
The use of low-speed general-purpose external memories in signal processing devices for electronic musical instruments leads to performance declines due to latency issues, especially when accessing data randomly, which is exacerbated by the need for shared memory and increased functionality in recent instruments.
Innovation Solution
Implementing a signal processing device with a first memory controller that reads and writes sampling data in sequential orders between internal and external memories, using a double buffer system for burst access to minimize latency and improve processing efficiency, thereby reducing the impact of external memory access delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external memory is used for signal delay processing, then device functionality and effect processing capacity are improved, but processing speed declines due to latency
Solution Approach 1:
The patent divides the external memory access into two separate controllers: a first memory controller that reads data from external memory in sequential order, and a second memory controller that writes processed data back to external memory. This segmentation allows the processing unit to operate independently without waiting for memory access completion, thereby maintaining high processing speed while using external memory for signal delay effects.
Solution Approach 2:
The patent introduces buffer memory as an intermediary between the processing unit and external memory. The first memory controller reads data from external memory into the buffer, and the second memory controller writes processed data from the buffer back to external memory. This intermediary buffer allows the processing unit to access data without direct latency penalties from external memory access, resolving the contradiction between using external memory for effects and maintaining processing speed.
2Adaptability or versatility
If random access is performed in external memory, then flexibility in data access is improved, but latency increases significantly
Solution Approach 1:
The first memory controller performs preliminary action by reading data from external memory in sequential order before the processing unit needs to access it. This prefetch mechanism ensures that data is already in the buffer when required, eliminating latency delays. The processing unit can then access data flexibly without suffering from external memory access time, resolving the contradiction between access flexibility and latency.
Solution Approach 2:
The patent implements periodic sequential access to external memory through the first and second memory controllers that operate in cycles: reading sequentially, processing, then writing sequentially. This periodic sequential access pattern replaces random access, maintaining data access flexibility while eliminating the latency penalties associated with random access in external memory.
3Productivity
If high-speed memory is used, then processing speed is improved, but device cost increases
Solution Approach 1:
The patent uses inexpensive external memory devices for signal delay processing instead of expensive high-speed internal memory. By implementing the dual memory controller architecture with sequential access patterns, the system achieves sufficient processing speed using cheaper external memory, thereby reducing device cost while maintaining acceptable performance.
Solution Approach 2:
The buffer memory acts as an intermediary that allows the system to use cheap external memory while achieving fast effective access speeds. The buffer cache frequently accessed data, making the external memory appear as fast as internal memory for practical purposes, thus avoiding the need to purchase expensive high-speed memory while maintaining good performance.
Data Source
AI summary
A double buffer (four pages×2 system) constituted by a DSP program buffer (D-RAM) and a prefetch program buffer (D-RAM) is provided, and burst access is performed collectively for four samplings from the prefetch program buffer (D-RAM). When this burst access is performed, a decline in performance caused by latency that occurs each time an external memory (DDR-SDRAM) is accessed is avoided by accessing with sequential addresses.