Signal Processing Circuit for Multi-Pulse GOA Driving

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current gate driver technologies, such as gate driving chips and Gate Driver on Array (GOA) circuits, face challenges in achieving a narrow bezel design and multi-pulse driving of gate lines in display devices, with GOA circuits unable to output multi-pulse signals and gate driving chips occupying significant space.

Innovation Solution

A signal processing circuit that combines single-pulse gate signals from multiple shift registers to produce a multi-pulse gate driving signal, facilitating the narrow bezel design and multi-pulse driving of gate lines by integrating with the GOA circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a gate driving chip is used to drive gate lines, then multi-pulse driving capability is achieved, but the occupied space increases significantly

Engineering Contradiction:
Improvemulti-pulse driving capabilityVSAvoidoccupied space
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent combines multiple shift registers (first shift register and second shift register) into a single integrated circuit structure that can be implemented on the array substrate. This merging approach enables multi-pulse driving capability while avoiding the need for a separate gate driving chip, thus reducing the occupied space while maintaining the adaptability for multi-pulse gate line driving.

Inventive Principle:
Principle #5Merging (Combining)

2Area of stationary object

If GOA circuit is used to drive gate lines, then narrow bezel design is enabled, but multi-pulse signal output is not achievable

Engineering Contradiction:
Improvebezel widthVSAvoidmulti-pulse signal output capability
Core Design Contradiction:
Area of stationary objectVSAdaptability or versatility

Solution Approach 1:

The patent introduces control signals (first control signal and second control signal) that dynamically switch the operating mode of the shift registers. By controlling the timing and sequence of these control signals, the circuit can dynamically generate multi-pulse outputs from the GOA structure, enabling both narrow bezel design and multi-pulse signal capability through dynamic signal manipulation rather than static circuit configuration.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If a single-pulse gate driving signal is output, then the circuit structure is simple, but pixel compensation cannot be performed

Engineering Contradiction:
Improvecircuit structureVSAvoidpixel compensation capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent employs periodic control signals that are applied in specific sequences to the shift registers. The first control signal and second control signal are activated at different time periods, creating a periodic pattern of pulse outputs. This periodic action enables the generation of multiple pulses required for pixel compensation while maintaining a relatively simple circuit structure that can be integrated into the display panel.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10636363B2Signal processing circuit and method for driving the same, display panel and display device
Publication Date: 2020.04.28 HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
  • US10636363B2 patent drawing
  • US10636363B2 patent drawing
  • US10636363B2 patent drawing

AI summary

Provided are a signal processing circuit and a method for driving the same, a display panel, and a display device. The signal processing circuit includes: an output circuit and a plurality of first input control circuits; each of the input control circuits has a corresponding pulse signal input terminal. All input control circuits and the output circuit are coupled at a first node. Each of the input control circuits may input a first operating voltage supplied from a first power supply terminal to the first node in certain cases. The output circuit may output an active-level voltage supplied from an active-level providing terminal or an inactive-level voltage supplied from an inactive-level providing terminal to the signal output terminal in certain cases.