Signal Processing Circuit Phase Adjusting Error Compensation
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Solution Overview
Problem
Conventional signal transceiving circuits face issues with echo interference and require complex error calculation circuits, which consume more area and resources, and sampling phase inaccuracies due to close phase alignment among components.
Innovation Solution
A signal processing circuit and method that utilize a first clock source, phase adjusting circuit to generate clock signals with different phases, an error compensating circuit to generate a compensated input signal, and an ADC to sample using a second clock signal, thereby simplifying the circuit and increasing phase differences between sampling components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If error detection is performed to compensate the input signal, then echo interference is reduced, but the circuit area and calculation complexity increase
Solution Approach 1:
The patent segments the error calculation process by using different clock signals (first clock signal for error calculation, second clock signal for sampling) and divides the circuit into specialized functional blocks. This segmentation allows the error calculating circuit to operate with reduced complexity while maintaining echo suppression effectiveness.
Solution Approach 2:
The patent changes the clock signal parameters by introducing multiple clock signals with different phases and timing characteristics. The first clock signal is used for error calculation while the second clock signal is used for sampling, allowing the circuit to achieve proper error compensation with simpler logic by changing the temporal parameters of operation.
2Productivity
If multiple components sample the same signal with close sampling phases, then signal processing is efficient, but sampling accuracy decreases
Solution Approach 1:
The patent implements periodic action by using clock signals with different phases for sampling operations. The first clock signal and second clock signal operate in periodic cycles with specific phase relationships, ensuring that multiple components sample at properly spaced intervals rather than simultaneously, thus maintaining both efficiency and accuracy.
Solution Approach 2:
The patent applies dynamics by making the sampling phases adjustable and differentiated. Instead of fixed simultaneous sampling, the circuit dynamically assigns different sampling phases to different components based on their functional requirements, allowing the system to adapt timing to maintain accuracy while preserving processing efficiency.
Data Source
AI summary
A signal processing circuit, which includes: a first clock source, configured to generate a first clock signal; a phase adjusting circuit, configured to receive the first clock signal, and to generate a second clock signal and a third clock signal, wherein the second clock signal and the third clock signal have different phases; an error compensating circuit, configured to compensate an input signal according to an error signal, to generate an compensated input signal; an error calculating circuit, configured to generate the error signal according to the first clock signal, the third clock signal and the compensated input signal; and a receiving end ADC (Analog to Digital Converter), configured to sample the compensated input signal according to the second clock signal.