Signal Processing Circuit Reset Control Origin Identification
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Solution Overview
Problem
The existing reset control systems, as described in patent literature 1, fail to function properly when applied to configurations where the information processing apparatus is not directly controlled by multiple central processing units issuing reset requests, leading to abnormal reset processes.
Innovation Solution
A signal processing system with a secondary arithmetic processing unit and a signal processing circuit that accepts reset requests from central processing units, using a control origin identification signal to determine the origin of the reset request and perform the reset process without interfering with processes initiated by different central processing units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reset control system from patent literature 1 is applied to a configuration where the information processing apparatus is not directly controlled by multiple central processing units, then the reset process cannot be performed normally, but the system structure becomes more complex and indirect control is required
Solution Approach 1:
The patent introduces a secondary arithmetic processing unit as an intermediary between the central processing units and the signal processing circuit. This mediator receives reset requests from multiple CPUs, identifies the control origin using a control origin identification signal, and determines whether to execute the reset process. This intermediary structure resolves the contradiction by enabling reliable reset operations in indirect control configurations while maintaining a manageable system architecture through clear separation of control functions.
2Reliability
If a reset request is transmitted from a central processing unit that is not currently operating, then the reset process may be blocked by AND circuits, but this blocking mechanism prevents proper reset execution
Solution Approach 1:
The patent implements preliminary identification of the control origin before the reset process is executed. The secondary arithmetic processing unit uses the control origin identification signal to determine in advance whether the transmitting CPU is the control origin before blocking or allowing the reset process. This preliminary action resolves the contradiction by enabling proper reset execution from non-operating CPUs while preventing unauthorized resets, replacing the overly restrictive AND circuit blocking mechanism with a more intelligent control approach.
3Reliability
If all flip-flops are set to '1s' to enable reception of reset requests from all central processing units, then reset requests can be received, but processes initiated by other central processing units may be hindered
Solution Approach 1:
The patent employs feedback mechanisms where the secondary arithmetic processing unit continuously monitors the control origin identification signal and the state of the signal processing circuit. Based on this feedback, the unit intelligently determines whether to execute the reset process or allow continuous operation. This feedback-based approach resolves the contradiction by enabling selective reset execution that maintains both reliable reset request reception and continuous process execution by other CPUs, avoiding the need to set all flip-flops to '1s' indiscriminately.
Data Source
AI summary
A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.