Signal Transmitter Readout Using Dual Serial Clocking
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Solution Overview
Problem
Existing technologies face challenges in efficiently reading out signal transmitters, particularly those using ENDAT 2.1 or ENDAT 2.2 protocols, without requiring additional timer units or interrupts, and are limited by conventional clock signal generation methods.
Innovation Solution
The readout device utilizes the first data output to generate a clock signal for both the signal transmitter and the second serial interface, allowing operation at a lower frequency, enabling oversampling and efficient communication using standard microcontrollers, and employs a signal converter device for level and signal transmission mode conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional clock signal generation methods are used with separate clock outputs, then reliable clocking is achieved, but device complexity increases and additional hardware is required
Solution Approach 1:
The first data output is designed to perform dual functions: transmitting data signals during normal operation and generating clock signals for the second serial interface and signal transmitter. This multi-functionality eliminates the need for separate dedicated clock output hardware, reducing device complexity while maintaining reliable clock signal generation.
Solution Approach 2:
The patent combines the data output function and clock signal generation function into a single hardware component (the first data output). By merging these previously separate functions, the system reduces the number of required hardware components and simplifies the overall device architecture.
2Speed
If the first serial interface operates at high clock frequency, then data transmission speed is improved, but measurement precision of time values decreases
Solution Approach 1:
The system segments the data transmission function into two separate interfaces: the first serial interface operates at high clock frequency for fast data transmission, while the second serial interface operates at the signal transmitter's clock frequency for precise time value measurement. This segmentation allows each interface to be optimized for its specific function without compromise.
Solution Approach 2:
The second serial interface acts as an intermediary for time value measurement. It receives the signal transmitter data signal at the same clock frequency as the transmitter operates, enabling accurate measurement of time values such as recovery times, while the first serial interface handles high-speed data transmission separately.
3Device complexity
If standard microcontrollers are used instead of FPGAs or microcontrollers with special peripherals, then device complexity is reduced, but adaptability to different protocols is limited
Solution Approach 1:
The dual serial interface configuration provides universal compatibility with different signal transmitter protocols. The second serial interface can be configured to match the clock frequency and communication protocol of various signal transmitters (e.g., ENDAT 2.1, ENDAT 2.2), while the first serial interface handles high-speed data transfer, enabling standard microcontrollers to adapt to multiple protocols.
Solution Approach 2:
The system achieves protocol adaptability by changing operational parameters: the second serial interface operates at the same clock frequency as the signal transmitter to ensure protocol compatibility, while the first serial interface operates at higher frequencies for efficient data transfer. This parameter adjustment allows standard microcontrollers to work with different protocols without requiring special peripherals.
Data Source
AI summary
A readout device for industrial automation, for reading out a signal transmitter. The readout device includes: a computing unit including a first serial interface and a second serial interface, in which the first serial interface has a first data output, a first data input and preferably a clock output, and the second serial interface has a second data output, a second data input and a clock input. The clock input is connected to the first data output and the computing unit is designed to output a clock signal at the first data output for clocking both the signal transmitter to be read out and the second serial interface, and to receive a signal transmitter data signal originating from the signal transmitter by means of the first data input and/or the second data input.