Signal Receiver Circuit With Negative-Voltage Sampling for Low-Voltage Inputs
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Solution Overview
Problem
In low-power systems using a low termination scheme, signal receiver circuits face challenges in recognizing low-voltage input signals due to the inferior performance of PMOS transistors compared to NMOS transistors, leading to reduced performance of strong arm latches.
Innovation Solution
A signal receiver circuit design that includes a negative voltage applier, sampling NMOS transistors, a precharger, an equalizer, and an amplifier, utilizing two clocks to manage voltage levels and current flow, allowing accurate sampling and amplification of low-voltage input signals while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If PMOS transistors are used to sample input signals in low-power systems with low termination scheme, then the circuit can operate with low power consumption, but the performance of the strong arm latch is reduced due to lower transistor performance
Solution Approach 1:
The patent changes the voltage parameter by applying a negative voltage to the common source node of the PMOS sampling transistors. This negative voltage shift increases the gate-source voltage difference, enhancing the transistor's ability to sink current and sample low-voltage signals effectively, thereby improving latch performance while maintaining low-power operation
Solution Approach 2:
The patent introduces a negative voltage generator as an intermediary component that provides a negative voltage to the common source node. This intermediary voltage source acts as a mediator to boost the sampling capability of PMOS transistors without requiring high-voltage input signals, resolving the contradiction between low power consumption and adequate sampling performance
2Productivity
If NMOS transistors are used for sampling input signals, then the strong arm latch performance is improved, but the circuit cannot properly recognize low-voltage input signals in low-power systems
Solution Approach 1:
The patent modifies the voltage parameter by applying negative voltage to enable PMOS transistors to properly sample low-voltage signals, achieving both good signal recognition and latch performance
Solution Approach 2:
Instead of using the conventional approach of NMOS transistors for sampling, the patent inverts the approach by using PMOS transistors with negative voltage applied to the common source node. This inversion allows PMOS transistors to effectively sink current from low-voltage sampling nodes, achieving proper signal recognition while maintaining low-power operation
Data Source
AI summary
A signal receiver circuit includes: a negative voltage applier suitable for applying a negative voltage to a common source node in response to a first clock is at a first logic level; a first sampling transistor coupled between the common source node and a first sampling node to sink a current from the first sampling node to the common source node in response to a first input signal; a second sampling transistor coupled between the common source node and a second sampling node to sink a current from the second sampling node to the common source node in response to a second input signal; an equalizer suitable for equalizing the first sampling node and the second sampling node in response to the first clock is at a second logic level; a precharger suitable for precharging a first output node and a second output node with a pull-up voltage in response to a second clock is at the first logic level, and electrically coupling the first output node and second output node to the second sampling node and the first sampling node, respectively, in response to the second clock is at the second logic level; and an amplifier suitable for amplifying a voltage difference between the first output node and the second output node in response to the second clock is at the second logic level.