Signal Recognition Circuit for Parallel Bit-Combination Decoding
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Solution Overview
Problem
The challenge lies in increasing data transmission rates beyond the limitations imposed by the speed of silicon CMOS transistors, as further miniaturization reaches physical limits, and existing bit-by-bit processing methods hinder high-speed data signal processing.
Innovation Solution
A signal processing circuit that generates output signals based on bit combinations from a plurality of bit signals, utilizing a distributed memory, ROM, and DAC, with a recognition circuit that includes determination stages and a serial-parallel converter to produce control signals for determining bit states, and an optical resonance circuit to modulate pulses, enabling processing without relying solely on transistor speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial-parallel conversion is used to process high-speed data signals with low-speed electric circuits, then the data transmission rate can be increased, but the processing speed is limited by the transistor speed which reaches physical limits due to further miniaturization
Solution Approach 1:
The patent segments the N-bit input signal into multiple groups of bits, where each group is processed by a separate determination circuit. This segmentation allows parallel processing of multiple bit groups simultaneously, increasing the overall data transmission rate without requiring each individual transistor to operate at higher speeds. The segmentation divides the processing task into manageable chunks that can be handled by existing transistor technology.
Solution Approach 2:
The patent transitions from sequential bit-by-bit processing to parallel group-based processing by adding a dimensional aspect to the processing architecture. Multiple determination circuits operate simultaneously on different bit groups, effectively moving from a one-dimensional sequential process to a multi-dimensional parallel process. This dimensional change enables the system to achieve higher throughput without increasing the speed of individual transistors.
2Speed
If the size of transistor gate channel is reduced to increase processing speed, then the transistor speed can be improved, but the miniaturization reaches physical limits making further speed increase difficult
Solution Approach 1:
Instead of relying on further miniaturization of the transistor gate channel, the patent segments the data processing into multiple parallel determination circuits. Each circuit processes a subset of bits, allowing the system to achieve higher effective processing speeds without requiring the physical gate channel to be made smaller than already feasible limits.
Solution Approach 2:
The patent replaces the mechanical approach of increasing transistor speed through physical miniaturization with an architectural approach using parallel processing. Rather than mechanically shrinking the gate channel to improve speed, the system uses multiple determination circuits working in parallel to achieve the same goal, substituting structural complexity for physical dimension reduction.
3Reliability
If bit-by-bit processing is used for high-speed data signals, then reliable processing can be achieved, but the processing speed is hindered and data transmission rate cannot be significantly increased
Solution Approach 1:
The patent segments the N-bit input into multiple groups and processes each group in parallel using separate determination circuits. This segmentation maintains the reliability of individual bit processing while achieving higher overall data transmission rates through parallel execution, resolving the contradiction between reliable processing and high productivity.
Solution Approach 2:
The patent combines multiple determination circuits to process different bit groups simultaneously. By merging these parallel processing units into a unified system that handles N-bit inputs, the patent achieves both the reliability of careful bit-by-bit processing and the high productivity of parallel operation, as each determination circuit reliably processes its assigned bits while contributing to the overall high-speed data transmission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased data transmission rates without reducing individual bit signal speeds, enabling the implementation of large-scale distributed memory, ultrahigh-speed ROM, and high-performance DAC, while maintaining processing efficiency.
Implementation Method 1
an optical resonance circuit to modulate pulses
Data Source
AI summary
A signal processing circuit is provided that generates output signals to be output from spatially different output ports based on bit combinations of an input word consisting of a plurality of bit signals. A distributed memory, a ROM and a DAC in which the signal processing circuit is used are also provided. A recognition circuit includes a serial port to which a bit signal is input and 2N output ports recognizing an input N-bit word and corresponding uniquely to 2N bit combinations. Output ports of the recognition circuit are connected to 2N input ports of an electric circuit. With no signal input to the recognition circuit, all outputs are constantly in a Low level state. In a case where a bit signal is input to the serial port of the recognition circuit, only one of the output ports corresponding to the bit combinations turns to a High level state.