Signal Sampling Circuit for Accurate DDR5 Command Decoding
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Solution Overview
Problem
In DDR5 DRAM, the Non-Target On-Die Termination Command (NT ODT CMD) signal, where the chip select signal is at a low level in two consecutive clock cycles, leads to erroneous decoding in the second clock cycle due to misinterpretation of the NT ODT CMD signal as a 2T CMD signal.
Innovation Solution
A signal sampling circuit with a clock processing circuit performing two-stage sampling and logical operations on the chip select signal, combined with a chip select control circuit for logical operations with the command signal, ensures accurate decoding by using the previous clock cycle's chip select signal for logic checks, preventing erroneous decoding in the second clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the chip select signal is at a low level in two consecutive clock cycles, then the NT ODT CMD signal can be properly transmitted, but erroneous decoding occurs in the second clock cycle due to misinterpretation as a 2T CMD signal
Solution Approach 1:
The patent applies preliminary action by performing two-stage sampling on the chip select signal before final decoding. The first sampling stage captures the chip select signal at the first clock edge, and the second sampling stage captures it at the second clock edge. This preliminary dual-sampling allows the system to distinguish between NT ODT CMD signals (low level in both cycles) and 2T CMD signals (low level only in first cycle) before the actual command decoding occurs, preventing erroneous decoding in advance.
Solution Approach 2:
The patent introduces an intermediary mechanism by using the chip select signal sampled at different clock edges as a mediator to differentiate between command types. The sampled chip select signals from two consecutive clock cycles serve as an intermediate verification step that mediates between the raw input signal and the final decoding decision, enabling accurate distinction between NT ODT CMD and 2T CMD signals without direct complex analysis of the command signal itself.
2Device complexity
If simple sampling is used for the chip select signal, then the circuit complexity is reduced, but decoding errors occur for NT ODT CMD signals
Solution Approach 1:
The patent applies segmentation by dividing the chip select signal sampling process into two distinct stages: first-stage sampling at the first clock edge and second-stage sampling at the second clock edge. This segmentation allows each stage to perform a specific function - the first stage captures the initial chip select state while the second stage verifies the continued low level, together providing reliable distinction between command types without requiring a single complex sampling mechanism.
Data Source
AI summary
A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock processing circuit, configured to perform two-stage sampling and logical operation on the to-be-processed chip select signal according to a first clock signal to obtain a chip select clock signal; a chip select control circuit, configured to perform sampling on the to-be-processed chip select signal according to the first clock signal to obtain an intermediate chip select signal, and perform logical operations on the intermediate chip select signal, the to-be-processed chip select signal and the to-be-processed command signal to obtain a command decoding signal; and an output sampling circuit, configured to perform sampling on the command decoding signal according to the chip select clock signal to obtain a target command signal.