Signal Sampling Circuit for Clock Feedthrough Noise Reduction
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Solution Overview
Problem
Current image sensors, particularly CMOS image sensors, face challenges with clock feedthrough and charge injection noise, which degrade image quality due to parasitic capacitors in MOS transistors, slowing down sampling speed and complicating fabrication processes.
Innovation Solution
A signal sampling circuit with a signal output unit, signal sampling unit, first current sinking unit, and second current sinking unit is designed to sample pixel signals during specific periods, using capacitors and transistors to maintain voltage levels and reduce noise by enabling the second current sinking unit after control signals are deactivated, thereby increasing sampling speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a MOS transistor is used as a switch in the signal sampling circuit, then the circuit can be fabricated using standard CMOS processes with low cost and low power consumption, but clock feedthrough and charge injection noise occur due to parasitic capacitors, degrading image quality
Solution Approach 1:
The patent extracts and removes the harmful parasitic capacitor from the signal path by introducing a separate sampling capacitor that is isolated from the transistor's gate-drain parasitic capacitance. The sampling capacitor captures the signal voltage without being affected by clock feedthrough, effectively separating the useful signal function from the harmful noise generation mechanism.
Solution Approach 2:
The patent introduces a floating diffusion node as an intermediary between the transistor output and the sampling capacitor. This intermediary isolates the parasitic capacitance effects from the signal sampling process, allowing the transistor to switch signals while the intermediary buffers against noise transmission to the sampling capacitor.
2Reliability
If the sampling period is extended to allow voltage stabilization, then noise from clock feedthrough is reduced, but sampling speed decreases
Solution Approach 1:
The patent performs preliminary signal transfer to the sampling capacitor during the integration period, before the reset switch closes. This preliminary action captures the signal voltage in advance, allowing the sampling to be completed quickly after the switch closes without waiting for slow voltage stabilization, thus maintaining high sampling speed while ensuring signal stability.
3Speed
If the reset switch closes quickly to increase sampling speed, then sampling rate increases, but voltage level instability occurs due to parasitic capacitor discharge
Solution Approach 1:
The patent extracts the voltage stabilization function from the main signal path by using a dedicated sampling capacitor that is charged through the reset switch. This separates the fast switching function (performed by the reset switch) from the voltage stabilization function (performed by the sampling capacitor), allowing the switch to close quickly without compromising voltage stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces noise caused by clock feedthrough, enhances sampling speed, and simplifies the fabrication process by stabilizing voltage levels quickly, improving image sensor performance and efficiency.
Implementation Method 1
The clock feedthrough or charge injection error refers to noise which occurs due to a parasitic capacitor CP existing between a gate and a drain of the MOS transistor or between the gate and a source of the MOS transistor
Data Source
AI summary
A signal sampling circuit includes: a signal output unit configured to output a level signal to an output node in response to a control signal; a signal sampling unit coupled to the output node and configured to sample the level signal in a sampling period; a first current sinking unit configured to sink a constant current from the output node; and a second current sinking unit configured to sink a current from the output node after a time point where the control signal is deactivated.