Signal Sampling Circuit for Multi-Mode DRAM Command Decoding
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Solution Overview
Problem
Existing DRAM chips require separate decoding circuits for different command modes, leading to large circuit area and decoding errors due to complex chip select signal changes.
Innovation Solution
A signal sampling circuit with a mode selection circuit, first and second clock processing circuits, and a command decoding circuit to distinguish and accurately decode 2T CMD and NT ODT CMD signals in different cycle modes, reducing circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate decoding circuits are arranged for command signals in different modes, then command decoding accuracy is improved, but circuit area increases
Solution Approach 1:
The patent merges the decoding functions for different command modes (2T CMD and NT ODT CMD) into a single shared decoding circuit. By using a mode selection circuit to generate different chip select clock signals based on the cycle mode, the same decoding circuit can accurately decode commands in both modes without requiring separate dedicated circuits for each mode, thus reducing circuit area while maintaining decoding accuracy.
Solution Approach 2:
The patent introduces dynamic mode selection that allows the decoding circuit to adapt its behavior based on the operating cycle mode. The mode selection circuit dynamically generates appropriate chip select clock signals (first chip select clock signal or second chip select clock signal) depending on whether the system is in 1N mode or 2N mode, enabling a single static decoding circuit to handle multiple operational modes correctly.
2Measurement precision
If separate decoding circuits are arranged for command signals in different modes, then command decoding accuracy is improved, but signal decoding confusion is reduced
Solution Approach 1:
The patent segments the signal processing into distinct stages: mode detection, mode selection, chip select clock generation, and command decoding. The mode selection circuit separates the handling of different cycle modes by generating mode-specific chip select clock signals, which then guide the decoding circuit to process commands appropriately for each mode, preventing signal decoding confusion while maintaining a unified decoding structure.
Solution Approach 2:
The patent introduces chip select clock signals as an intermediary between the mode selection circuit and the decoding circuit. These intermediary signals carry mode-specific timing information that guides the decoding process, allowing the decoding circuit to distinguish between different command modes without requiring separate decoding paths, thus reducing complexity while maintaining accuracy.
3Measurement precision
If mode-specific chip select clock signals are generated, then command distinction accuracy is improved, but power consumption increases
Solution Approach 1:
The patent uses periodic chip select clock signals with different characteristics for different modes. The mode selection circuit generates first chip select clock signals for 2T CMD in 1N mode and second chip select clock signals for NT ODT CMD in 2N mode. These periodic signals enable accurate command distinction while being generated only when needed for decoding operations, rather than continuously, thus limiting power consumption increases to only the active decoding periods.
Data Source
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AI summary
The embodiments of the present disclosure provide a signal sampling circuit and a semiconductor memory device. The signal sampling circuit includes a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a mode selection circuit, configured to determine a target mode clock signal and a target mode chip select signal according to the mode selection signal; a first clock processing circuit, configured to perform sampling and logic operation on the to-be-processed chip select signal and the target mode chip select signal according to the target mode clock signal, to obtain a first chip select clock signal; a second clock processing circuit, configured to perform sampling and logic operation on the to-be-processed chip select signal and the target mode chip select signal according to the target mode clock signal, to obtain a second chip select clock signal; and a command decoding circuit, configured to determine a target command signal.