Two-Stage Signal Sampling Circuit for Stable Command Pulse Width
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Solution Overview
Problem
The uncertainty in the pulse width of decoded signals in semiconductor memory devices leads to data failures, affecting performance, particularly in high-frequency environments and under variations in process, voltage, and temperature.
Innovation Solution
A signal sampling circuit with a clock receiving circuit for frequency division, a sampling and logic circuit for two-stage sampling, and a decoding circuit to generate a target command signal with precise pulse width, ensuring stability across process, voltage, and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single-stage sampling is used for command signals, then the circuit structure is simple, but the pulse width of decoded signals becomes uncertain leading to data failures
Solution Approach 1:
The sampling process is divided into two distinct stages: first-stage sampling captures the command signal at the first clock edge, and second-stage sampling refines the signal at the second clock edge. This segmentation allows precise control over pulse width generation, ensuring reliability while managing circuit complexity through modular design
Solution Approach 2:
The first-stage sampling performs preliminary capture of the command signal before the second-stage refinement. By pre-sampling the signal with a controlled pulse width in the first stage, the circuit establishes a reliable timing foundation that prevents data failures before the final decoding occurs
2Productivity
If higher data transmission speed is pursued, then productivity increases, but signal pulse width uncertainty worsens affecting data integrity
Solution Approach 1:
The circuit utilizes periodic clock signals with specific edge timing to sample commands. The regular periodic nature of the clock edges provides consistent timing references that maintain signal integrity even at higher transmission speeds, preventing pulse width uncertainty from degrading data quality
3Manufacturing precision
If dual-stage sampling is implemented, then pulse width precision is improved, but the circuit complexity increases
Solution Approach 1:
The sampling and logic circuit merges the two sampling stages with integrated logic operations that share common clock signals and control pathways. This combining approach achieves precise pulse width control through coordinated staging while reducing overall circuit complexity by eliminating redundant components and synchronizing operations
Data Source
AI summary
A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock receiving circuit, configured to receive an initial clock signal and perform frequency division processing on the initial clock signal to obtain a first clock signal; a sampling and logic circuit, configured to perform two-stage sampling processing and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a chip select clock signal, where the chip select clock signal includes two pulses, and the width of each pulse is a preset clock cycle; and a decoding circuit, configured to perform decoding processing and sampling processing on the to-be-processed command signal according to the to-be-processed chip select signal and the chip select clock signal to obtain a target command signal.