Signal Shifting Circuit for Phase Synchronization in Stacked Semiconductor Systems
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Solution Overview
Problem
In semiconductor systems with stacked chips, phase differences between internal clocks and data strobe signals can lead to errors in data recognition due to varying transmission speeds, reducing margins and affecting signal synchronization.
Innovation Solution
A signal shifting circuit that generates shifted bank selection signals by synchronizing them with multiple reference clocks of gradually changing phases, using a bank selection signal generation unit and shifting device to advance the phase of the signals, ensuring synchronization with a leading clock phase, thereby reducing phase differences and errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data and data strobe signal are transmitted through different transmission lines from base chip to core chips, then transmission speed differences cause phase differences between internal clock and data strobe signal, but this is necessary for parallel transmission to multiple core chips
Solution Approach 1:
The patent segments the signal transmission path by introducing intermediate buffer units in each core chip. These buffers receive the data strobe signal from the base chip, hold it temporarily, and then retransmit it to the appropriate memory banks. This segmentation allows the base chip to transmit signals in parallel to multiple core chips while each core chip independently manages its own signal timing, thereby maintaining synchronization accuracy despite transmission speed differences across multiple transmission lines.
Solution Approach 2:
The patent applies preliminary action by having the base chip transmit the data strobe signal to all core chips in advance, before the actual data write operation begins. The signal is transmitted through dedicated transmission lines to all core chips simultaneously, and then each core chip's buffer unit holds the signal until it is needed for the specific memory bank operation. This preliminary transmission ensures that all core chips receive the synchronization signal early, allowing them to prepare their internal timing without waiting for sequential signal propagation.
2Ease of operation
If data strobe signal is transmitted to all core chips through base chip, then phase difference between internal clock and data strobe signal reduces margin, but this enables centralized control of memory operations
Solution Approach 1:
The patent applies local quality by giving each core chip its own buffer unit specifically dedicated to handling the data strobe signal timing. Instead of relying on a single centralized timing mechanism at the base chip, each core chip has localized buffering capability that allows it to independently adjust and maintain optimal signal margins for its specific memory banks. This local quality enhancement ensures that even though the base chip transmits signals to all core chips, each core chip can locally optimize its signal timing to maintain adequate margins.
3Reliability
If bank selection signal is shifted multiple times according to latency information, then phase advancement reduces synchronization error, but this increases circuit complexity
Solution Approach 1:
The patent merges the bank selection signal shifting function with the existing latency control mechanism. Instead of adding separate shifting circuits for each bank selection signal, the invention combines the shifting operation with the latency information that is already being used for memory timing control. The buffer units that are already present for data timing adjustment are also used to perform the bank selection signal shifting by controlling their enable inputs based on the same latency information. This merging approach achieves the required phase advancement while avoiding additional circuit complexity.
Data Source
AI summary
A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.