Multi-Channel Signal Timing Control for Semiconductor Testing
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Solution Overview
Problem
Existing semiconductor testing apparatuses face challenges in synchronizing multiple signal generators to test high-speed semiconductor devices efficiently, requiring a leading device to wait for the most delayed device, which prolongs test time.
Innovation Solution
A semiconductor testing apparatus with a signal generation controller that compiles basic timing and pattern information into data signals, allowing independent timing adjustment of each signal generator using dummy times, eliminating the need for repeated signal generation and compilation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If synchronization is achieved by making a leading device wait until the most delayed device completes signal generation, then synchronization accuracy is improved, but test time increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and setting dummy times for each signal generator before actual signal generation begins. The controller determines the time difference between the leading and most delayed devices in advance, and configures each device's dummy time accordingly. This allows all devices to start signal generation simultaneously without the leading device needing to wait, thereby maintaining synchronization accuracy while reducing test time.
2Productivity
If dummy times are set for each signal generator to adjust timing independently, then test efficiency is improved, but device complexity increases
Solution Approach 1:
The patent introduces a controller as an intermediary that manages the complexity of dummy time configuration. Rather than requiring complex internal timing mechanisms in each signal generator, the controller centrally calculates and sets appropriate dummy times for each device based on their individual characteristics. This external mediation simplifies the internal structure of signal generators while maintaining overall system efficiency through coordinated timing control.
Data Source
AI summary
The semiconductor testing apparatus according to an embodiment includes a plurality of signal generators that apply a test signal to each of a plurality of IF of a device under test, and a signal generation controller that compiles a signal including basic timing information and pattern information for a test item to be measured into a data signal, and performs timing adjustment of the test signal by setting timing information based on the data signal.