Signal Transfer Circuit Timing Adjustment for Bus Master Scalability
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Solution Overview
Problem
The existing signal transfer protocols in system large-scale integrations (LSIs) for image processing apparatuses face challenges in managing strict timing requirements between arbiters and bus masters, leading to difficulties in increasing the number of embedded bus masters and speeding up operation clocks due to signal delays and increased circuit complexity.
Innovation Solution
A signal transfer circuit is introduced between bus masters and arbiters to adjust the timing of access requests, memory addresses, and data signals, allowing for earlier output of control and data signals, thereby alleviating signal delays and maintaining protocol compliance even with increased bus master count and faster clock speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of embedded bus masters is increased to improve processing capability, then the system performance is improved, but the signal delay between arbiters and bus masters increases due to longer wiring and more circuit stages
Solution Approach 1:
The patent applies preliminary action by outputting the acknowledge signal and data enable signal one clock cycle earlier than traditionally required. The arbiter outputs these control signals in advance, allowing bus masters to begin data transmission earlier. This advance timing compensates for the increased signal propagation delay caused by adding more bus masters, thereby maintaining protocol compliance while enabling higher system throughput.
Solution Approach 2:
The patent segments the data transmission process into distinct phases with independent timing control. By separating the control signal timing (acknowledge and data enable) from the data payload timing, the system can optimize each phase independently. This segmentation allows the control signals to be transmitted with adjusted timing to compensate for wiring delays, while data transmission follows the established protocol, thus supporting more bus masters without compromising reliability.
2Speed
If the operation clock speed is increased to improve system performance, then the processing speed is improved, but the timing margin for signal transfer becomes insufficient due to fixed protocol requirements
Solution Approach 1:
The patent enables higher clock speeds by performing preliminary action with control signals. The arbiter outputs acknowledge and data enable signals one clock cycle earlier, creating additional timing margin that absorbs the reduced setup time available at higher frequencies. This allows the system to operate at faster clock speeds while still meeting the minimum timing requirements of the protocol for data validation and processing.
3Adaptability or versatility
If the wiring length between arbiters and bus masters is increased to accommodate more bus masters, then the system scalability is improved, but the signal delay and circuit complexity increase
Solution Approach 1:
The patent addresses scalability issues by applying preliminary action to control signal timing. Rather than redesigning the physical layout or reducing the number of bus masters, the arbiter compensates for increased wiring delay by advancing the output timing of control signals. This timing adjustment maintains signal integrity and protocol compliance across extended wiring lengths, enabling system scalability without proportionally increasing circuit complexity.
4Reliability
If the timing of control signals is advanced to compensate for signal delay, then the signal transfer reliability is improved, but the risk of premature signal output may occur
Solution Approach 1:
The patent implements controlled preliminary action by advancing control signal output by exactly one clock cycle, which is the minimum increment required to compensate for wiring delays. This precise timing adjustment improves signal transfer reliability by ensuring that signals arrive with adequate setup time, while the one-cycle advancement limit prevents excessive early output that could cause timing conflicts or premature data validation before data is actually ready.
Data Source
AI summary
A signal transfer circuit comprising a control signal transfer unit configured to output an access request output signal and a memory address output signal to the arbiter after timings of the access request input signal of the access request and the memory address input signal input from the bus master have been adjusted, and output an access permission output signal, and a data signal transfer unit configured to output each data output signal to the corresponding bus master or the arbiter after a timing of each data input signal of the access request input from the arbiter or the bus master is adjusted, and output a data validity period output signal to the bus master after a timing of a data validity period input signal indicating a period in which each data is valid in the access request input from the arbiter is adjusted.