Reception Signal Validity Testing with Dummy Parity Bit Decoding

The patent segments the error detection and correction function into distinct layers: polar code for error correction and outer codes (CRC/PC) for error detection. Each layer handles specific aspects of signal validation, allowing the system to determine signal validity through structured multi-layer verification rather than a single complex mechanism.

The patent introduces dummy parity bits as intermediary elements that facilitate coordination between the polar code decoder and outer code validators. These dummy bits act as mediators that carry validation information through the decoding process, enabling the receiver to distinguish between actual signal errors and validation artifacts without increasing operational complexity.

The patent applies preliminary action by performing polar code decoding first to correct errors in the received signal, then sequentially applying outer code validation (CRC followed by PC). This ordering allows the most powerful error correction mechanism to operate first, reducing the burden on subsequent validation stages and minimizing total processing time while maintaining high measurement precision.

The patent implements partial action by conditionally applying outer code validation only when needed. The system uses the polar code decoder's intrinsic validation capabilities for basic error detection, and only invokes the more time-consuming outer code checks when the signal shows signs of corruption or when validation is specifically required, thus balancing precision with processing efficiency.