Signal Transmission Circuit Using Virtual Lanes for Line Reduction
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Solution Overview
Problem
Conventional serialized signal transmission in D-PHY interfaces is error-prone and unstable, particularly in reducing the number of lines required for data transmission between mobile device components like cameras and displays.
Innovation Solution
A circuit arrangement and method that serialize single-ended High Speed data and differential Low Power data into a common signal stream using a multiplexer and demultiplexer, with the clock embedded within the signal stream, and introduce a virtual lane for Low Power data to maintain error-free and stable transmission without expanding the coding space for High Speed data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional serialized signal transmission is used to reduce the number of transmission lines, then the number of lines is reduced, but the transmission becomes error-prone and unstable
Solution Approach 1:
The invention segments the transmission medium into multiple virtual lanes (at least two virtual lanes) within the single physical transmission line. This allows separate serialization of High Speed data and Low Power data into distinct virtual channels, enabling independent error handling and stability maintenance for each data type while reducing the overall number of physical lines required.
Solution Approach 2:
The invention introduces a clock signal as an intermediary element that is serialized together with the data into the common signal stream. This embedded clock serves as a reference for the receiving end to accurately reconstruct and separate the data from different virtual lanes, ensuring stable and error-free transmission despite the reduced number of physical lines.
2Quantity of substance
If High Speed and Low Power data are bundled into a common serial stream, then line reduction is achieved, but the coding space for High Speed data must be expanded
Solution Approach 1:
The invention divides the common serial signal stream into multiple virtual lanes, with at least one virtual lane dedicated to High Speed data and another to Low Power data. This segmentation allows each data type to maintain its original coding scheme without requiring expansion of the coding space for High Speed data, while still achieving line reduction through physical consolidation.
Solution Approach 2:
The invention adds the dimension of virtual lane separation within the single physical transmission line. By organizing data transmission in the virtual lane dimension rather than requiring additional physical lines, the system achieves line reduction without increasing the coding complexity for High Speed data.
3Reliability
If single-ended High Speed data and differential Low Power data are transmitted separately, then data integrity is maintained, but the number of transmission lines increases
Solution Approach 1:
The invention merges single-ended High Speed data and differential Low Power data into a common serialized signal stream transmitted over a single physical line. By maintaining separate virtual lanes for each data type with dedicated serialization processes, the system preserves data integrity while reducing the number of physical transmission lines required.
Solution Approach 2:
The single physical transmission line is designed to be universal, capable of carrying both High Speed data and Low Power data through different virtual lanes. This multi-functionality allows one physical line to replace multiple separate lines, reducing the overall quantity of transmission lines while maintaining the reliability needed for different data types.
Data Source
Figure 1A~1B
Figure 1C
Figure 2A~2B
AI summary
The invention relates to a circuit arrangement (S, E) and to a corresponding method, using single-ended signals based on logic levels and differential, in particular common mode based signals, in which a serialized signal is continually transmitted in an accurate and stable manner.