Signature Generation Apparatus Single-Bus Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing group signature generation and verification technologies require high-speed processing but result in increased manufacturing costs due to complex multi-layered electronic circuit designs.
Innovation Solution
A signature generation and verification apparatus with a single IP core architecture that includes fast arithmetic units, a data transfer controller, and a narrow-band local bus, allowing for parallel computation and reduced circuit complexity, thereby accelerating group signature processing while minimizing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multi-layered electronic circuit design is used to increase bandwidth for information exchange, then operation speed is improved, but manufacturing cost increases
Solution Approach 1:
The patent segments the signature generation and verification functions into dedicated functional units (signature generation unit with computing units 21-24, signature verification unit with computing units 31-34) that operate independently. This segmentation allows each unit to be optimized for its specific function while sharing common infrastructure (single bus 14, control unit 10), reducing overall circuit complexity and manufacturing cost compared to fully multi-layered designs.
Solution Approach 2:
The patent implements a universal single bus 14 that serves multiple functions: data input, data output, and inter-unit communication for both signature generation and verification operations. The control unit 10 universally manages both generation and verification processes. This multi-functional approach eliminates the need for separate dedicated buses for each function, reducing circuit layers and manufacturing cost while maintaining high-speed operation.
2Productivity
If complex multi-layered electronic circuit design is implemented, then processing capability is improved, but device complexity increases
Solution Approach 1:
The patent divides the processing capability into specialized functional segments: signature generation unit (20) with computing units 21-24 for generation operations, and signature verification unit (30) with computing units 31-34 for verification operations. Each segment is optimized for its specific cryptographic operations (elliptic curve computations, modular arithmetic) while sharing the common bus 14 and control unit 10, achieving high processing capability without proportionally increasing overall circuit complexity.
Solution Approach 2:
The patent merges the signature generation and verification functions into a single integrated device that shares common infrastructure: the single bus 14 for data transfer, the control unit 10 for operation management, and similar computing unit architectures (21-24 for generation, 31-34 for verification). This merging reduces device complexity compared to implementing separate multi-layered circuits for each function, while maintaining high processing capability through parallel operational capability.
Data Source
AI summary
A signature generation apparatus generates a signature for a message m from the i-th user, and computes any two or three of a[1]μ[x] (mod n), a[2]μ[s] (mod n), and wμ[t] (mod l) are in parallel. For this reason, the signature generation apparatus is provided with a plurality of fast arithmetic units (sub-IPs) within the IP core. The individual sub-IPs are connected to each other via a narrow-band, single-layer local bus.