Signature Generators for Encrypted Memory Error Injection Detection
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Solution Overview
Problem
Existing methods for detecting error injection in microprocessor architectures, such as dual modular redundant architectures, face challenges including increased space requirements and vulnerability to attacks, particularly in resource-constrained systems like smart-cards.
Innovation Solution
An apparatus and method utilizing signature generators to create processed keys from processor instructions, employing XOR operations to access encrypted memory portions, allowing for efficient detection of control flow changes and immediate invalidation of data in case of attacks, without relying on redundant processor architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual modular redundant architectures are employed to detect error injection, then security detection capability is improved, but space requirements and device complexity increase
Solution Approach 1:
Instead of fully replicating the processor architecture, the patent creates a simplified copy that only replicates the instruction execution path and signature generation logic. This partial copying approach maintains detection capability while reducing the complexity and space requirements of the redundant architecture.
Solution Approach 2:
The patent segments the security verification function into separate signature generators that operate independently on instruction streams. This allows the detection mechanism to be distributed and modular, reducing the complexity of any single component while maintaining overall detection capability.
2Reliability
If dual modular redundant architectures with pre-computed signatures are used, then error detection is improved, but additional memory space is required
Solution Approach 1:
The patent performs preliminary signature generation during instruction execution rather than requiring pre-computed signatures to be stored in memory. The signatures are generated on-demand by the signature generators as instructions are fetched and executed, eliminating the need for large memory allocations to store pre-computed signature tables.
3Reliability
If comparison logic or voter is added to dual modular redundant systems, then error detection is improved, but the system becomes more vulnerable to attacks
Solution Approach 1:
The patent extracts the verification function from a centralized comparison logic and distributes it across multiple signature generators that independently verify instruction execution. This eliminates the single point of vulnerability that would exist in a centralized voter or comparison unit, as each signature generator operates independently and can detect anomalies without requiring trust in a central authority.
4Reliability
If complete replication of processor unit is performed, then security verification is improved, but space requirements double
Solution Approach 1:
The patent applies local quality by implementing verification only in the specific regions where security is most critical - the instruction fetch and execution path. Rather than replicating the entire processor unit, signature generators are placed strategically at key points in the instruction stream to verify critical operations, reducing the overall space requirement while maintaining security effectiveness.
Data Source
AI summary
An apparatus for accessing an encrypted memory portion of a memory is provided. The apparatus includes a plurality of signature generators, wherein each signature generator of the plurality of signature generators is configured to generate a signature of a plurality of signatures depending on an instruction of a plurality of instructions, wherein each of the plurality of instructions is a processor instruction for controlling a processor. Moreover, the apparatus includes a key modifier for generating a processed key depending on a standard key and on the plurality of signatures. Furthermore, the apparatus includes a controller for accessing the encrypted memory portion of the memory, wherein the memory access controller is configured to employ the processed key to access the encrypted memory portion of the memory.