Signature-Based Layout Verification for IC Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of semiconductor IC designs and layouts results in larger data files, making traditional layout-versus-layout (LVL) comparisons using Boolean exclusive-or (XOR) operations inefficient in terms of computing resources and processing time.
Innovation Solution
Generating and comparing signatures of IC layouts instead of the layouts themselves, allowing for efficient LVL comparison without the need for expensive CAD tools, by breaking down layouts into basic elements and hierarchical cells, and using hashing methods to create unique signatures for each element and cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional Boolean XOR operation is used for layout comparison, then comparison accuracy is maintained, but computing resources and processing time increase significantly
Solution Approach 1:
The layout is segmented into hierarchical cells and basic elements, each assigned a unique signature. The comparison is then performed on these signatures rather than the entire layout, dividing the complex comparison task into smaller, manageable units that can be processed more efficiently.
Solution Approach 2:
Instead of comparing the actual layout data directly, the patent creates and compares signatures (hash values) that represent the layouts. These signatures are simpler data structures that capture the essential characteristics of the layouts without requiring processing of the full layout complexity.
2Adaptability or versatility
If layout data files are made larger to accommodate increased integration, then design capability is improved, but computing resource consumption increases
Solution Approach 1:
The patent creates a compressed representation (signature) of the layout data that captures all necessary information for verification without requiring the full original data. This signature can be stored and processed with minimal memory requirements, eliminating the need to keep large layout files in memory during comparison operations.
Solution Approach 2:
The essential characteristics of the layout are extracted into the signature, separating the verification function from the storage requirement. The signature contains only the information needed for comparison, while the full layout data can be stored separately without impacting the computing resources required for verification.
3Reliability
If layout verification is performed on complex IC designs, then design verification accuracy is maintained, but processing time increases
Solution Approach 1:
The layout is pre-processed into hierarchical cells with assigned signatures before the actual verification process. This preliminary organization of data into signed structures enables rapid comparison during verification without requiring time-consuming analysis of the complex layout during the verification step itself.
Solution Approach 2:
The verification process is segmented by comparing signatures of hierarchical cells rather than processing the entire complex layout at once. This segmentation allows the verification system to handle complex designs by breaking them down into manageable units that can be verified in parallel or sequentially with minimal time overhead.
Data Source
AI summary
Methods and apparatus of performing layout-versus-layout (LVL) comparison are disclosed. A layout may be in various formats such as GDSII or OASIS, for different circuits, and represented by a basic layout element, a hierarchical cell or a plurality of independent cells in various layers. A basic layout element, a hierarchical cell, and a layout with a plurality of independent cells may have a signature generated according to the embodiment methods. The signature of a basic layout element may be generated based on values of a center and a circumference, and a hashed trace value generated by a hash function of a trace of the basic layout element. The signature of a hierarchical cell can be generated recursively. A signature of a first layout may be compared to a signature of a second layout to determine whether the first layout matches the second layout.