Signed Bit Slice Generator for AI Neural Network Accelerators
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Solution Overview
Problem
Conventional bit slice hardware architectures for AI neural networks face limitations in improving performance with 2's complement data, particularly due to limited utilization of sparsity in negative data, high output speculation errors, and large logic area requirements, especially when dealing with 2's complement data.
Innovation Solution
The solution involves generating signed bit slices with the same length, including a sign bit, which eliminates the need for sign extension, allows for increased data compression and calculation speed, and reduces power consumption by utilizing sparsity in both positive and negative data near zero, and symmetrizing bit slice values to minimize speculation errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit slice hardware architecture is used to skip calculation of bit slices with value 0, then calculation speed is improved for positive data, but performance improvement is limited for negative data near 0 in 2's complement representation
Solution Approach 1:
The patent transforms the representation parameters of bit slices by adding a sign bit to each bit slice, changing them from unsigned to signed representation. This parameter change enables the system to properly represent and exploit sparsity in negative data near zero in 2's complement form, while maintaining the ability to skip zero-valued bit slices for computational speedup.
2Productivity
If output value is predicted by first calculating upper bit slice, then remaining lower bit slice calculation is skipped, then calculation speed is improved, but speculation errors increase due to asymmetry in 2's complement data distribution
Solution Approach 1:
The patent addresses the asymmetry problem by making bit slice values symmetric through sign extension. By adding sign bits to lower bit slices, the representation becomes symmetric around zero, reducing speculation errors when predicting output values from upper bit slice calculations alone.
3Productivity
If data skipping is performed for all bit slices, then calculation speed is improved, but logic area increases due to requiring as much skipping logic as the number of bit slices
Solution Approach 1:
The patent merges the sign bit information into each bit slice representation, allowing the skipping logic to operate on signed values directly. This integration eliminates the need for separate sign extension logic and combines multiple functions (sign representation, value comparison, skipping decision) into a unified bit slice processing unit, reducing overall logic area.
4Device complexity
If lower bit slice does not have sign bit unlike upper bit slice, then hardware complexity is reduced, but code extension logic is additionally required to add sign
Solution Approach 1:
The patent segments the sign bit information and distributes it to each bit slice independently. Instead of having only the upper bit slice contain the sign bit, each bit slice gets its own sign bit through sign extension, creating homogeneous signed segments that can be processed independently without additional extension logic.
Data Source
AI summary
A signed bit slice generator includes a divider configured to divide input data, which is 2's complement data having N (where N is a natural number)-bit precision, and divide remaining bits excluding a sign bit of the input data into a predetermined number of bit slices, a sign bit adder configured to add a sign bit to each of the bit slices, a sign value setter configured to set a sign bit of an MSB slice among the bit slices to a sign value of the input data and to set sign bits of the remaining bit slices to positive sign values, and a sparse data compressor configured to perform sparse data compression on each of the signed bit slices, thereby generating a predetermined number of signed bit slices having the same number of bits where each bit slice includes a sign bit.