Signed Return-to-Zero DAC for Correlated Edge Switching
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Solution Overview
Problem
High-speed digital-to-analog converters (DACs) in RF systems suffer from duty cycle errors and even order distortion due to uncorrelated rising and falling edges, leading to performance degradation.
Innovation Solution
Implementing a signed return-to-zero DAC with dynamic element matching (DEM) and using the same DAC cells for up and down transitions to correlate rising and falling edges, reducing second harmonic distortion and improving spurious free dynamic range (SFDR).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If unsigned current steering DACs operate at high signal frequencies, then conversion speed is improved, but duty cycle errors and even order distortion increase due to uncorrelated rising and falling edges
Solution Approach 1:
The patent applies asymmetry by using different DAC cell configurations for rising edges versus falling edges. Specifically, different sets of DAC cells are selected based on the transition direction, allowing the system to compensate for the inherent asymmetry in rising and falling edge behavior at high frequencies, thereby reducing even order distortion while maintaining high conversion speed
Solution Approach 2:
The patent implements dynamic element matching (DEM) algorithms that dynamically select and swap DAC cells based on transition direction and previous state. This dynamic reconfiguration allows the system to adapt to high-frequency operation by correlating rising and falling edges through intelligent cell selection, improving duty cycle accuracy without sacrificing conversion speed
2Adaptability or versatility
If different DAC cells are used for rising and falling edges, then transition flexibility is improved, but even order distortion increases due to uncorrelated edges
Solution Approach 1:
The patent employs feedback through dynamic element matching algorithms that monitor transition direction and previous DAC cell selections. The system uses this feedback to intelligently swap DAC cells between rising and falling edges, ensuring correlation between opposite transitions. This feedback mechanism reduces even order distortion while preserving the flexibility to handle various transition scenarios
Solution Approach 2:
The patent applies preliminary action by pre-planning DAC cell selections based on anticipated transition directions. The DEM algorithm prepares and selects appropriate DAC cells in advance of the actual signal transition, ensuring that correlated cells are ready for rising or falling edges. This preliminary selection process reduces distortion by preventing uncorrelated edge behavior while maintaining transition flexibility
Data Source
AI summary
Described herein are systems and methods related to a converter including a first input, a second input, and a number of digital to analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a return to zero operation. The DAC cell is configured to provide a data magnitude at a polarity on at least one of the first leg or the second leg during at least a portion of the clock cycle. The data magnitude and the polarity being provided in accordance with a first signal at the first input and a second signal at the second input.