Rounding Circuitry for Signed Digit Conversion
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Solution Overview
Problem
Existing data processing technologies face inefficiencies in rounding operations due to the need for complex addition circuitry and high power consumption, particularly when converting between redundant and non-redundant representations of signed digits.
Innovation Solution
A data processing apparatus and method that adjusts a subset of digits in the unrounded output value based on the value of the least-significant bit, allowing for efficient rounding without full addition circuitry, by selecting between the unrounded and incremented unrounded output values when the least-significant bit is greater than or equal to half the radix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional rounding circuitry is used to convert signed digits, then rounding accuracy is achieved, but device complexity and power consumption increase due to full addition circuitry requirements
Solution Approach 1:
The patent segments the rounding operation into two distinct parts: (1) generating candidate output values by adjusting only the least-significant digit based on extra bits, and (2) selecting the appropriate candidate using simple comparison logic. This segmentation eliminates the need for full addition circuitry while maintaining rounding accuracy, directly resolving the contradiction between precision and complexity.
Solution Approach 2:
Instead of performing a complete addition operation across all digits, the patent applies partial action by only adjusting the least-significant digit with a candidate value. This partial adjustment is sufficient to achieve rounding when combined with the selection step, reducing circuit complexity while preserving accuracy.
2Reliability
If full addition circuitry is implemented for rounding operations, then complete digit adjustment is achieved, but power consumption increases
Solution Approach 1:
The rounding process is divided into candidate generation and selection phases. The candidate generation phase only requires simple digit adjustment and comparison operations, avoiding power-intensive full addition circuitry. This segmentation maintains rounding correctness while significantly reducing power consumption.
Solution Approach 2:
The patent uses disposable candidate values that are generated, compared, and discarded in a single operation cycle. Instead of maintaining complex addition circuitry, simple candidate adjustments are performed and then abandoned after selection, reducing both power consumption and hardware complexity while ensuring correctness through systematic candidate evaluation.
3Measurement precision
If conventional rounding methods are used, then accurate rounding is achieved, but processing speed decreases due to complex circuit operations
Solution Approach 1:
By segmenting rounding into candidate generation and selection steps, the patent eliminates time-consuming full addition operations. The candidate generation uses simple digit adjustments that can be performed in parallel, and the selection step uses straightforward comparison logic, thereby maintaining precision while accelerating processing speed.
Solution Approach 2:
The patent performs preliminary candidate value generation before the final selection step. By pre-computing candidate values through simple digit adjustments rather than waiting for complete addition operations, the system accelerates the rounding process while ensuring precision through subsequent selection based on extra bit analysis.
Data Source
AI summary
A data processing apparatus is provided to convert a plurality of signed digits to an output value. Receiver circuitry receives, at each of a plurality of iterations, one of the plurality of signed digits, each of the signed digits comprising a number of bits dependent on a radix. The signed digits being used to form an unrounded output value followed by zero or more extra bits. Adjustment circuitry adjusts a least-significant digit of the unrounded output value to produce an incremented unrounded output value after the plurality of iterations. Rounding circuitry selects from among the unrounded output value and the incremented unrounded output value to produce the output value. The adjustment circuitry is adapted, when a value of a position of a least-significant bit of the unrounded output value is greater than or equal to the radix divided by two, to adjust a subset of the digits of the unrounded output value.