In-Memory Signed Element Compare via Sensing Circuitry
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face inefficiencies in performing signed element comparisons and logical operations, particularly in terms of power consumption and parallel processing capabilities, due to the need for extensive data transfer and the limitations of external processing resources.
Innovation Solution
The implementation of sensing circuitry within the memory array that performs signed element comparisons and logical operations directly on data stored in memory cells, using a reduced number of temporary storage rows and enabling operations like XOR and XNOR without intermediate results, while conforming to the pitch rules of memory cells, thereby reducing power consumption and enhancing parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between external processing resources and memory array, then processing operations can be performed, but power consumption increases and processing speed decreases
Solution Approach 1:
The patent combines processing resources with memory by implementing sensing circuitry that performs logical operations directly within the memory array. This merging eliminates the need for data transfer between separate memory and processing units, thereby reducing power consumption and improving processing speed simultaneously.
Solution Approach 2:
The memory array performs processing operations on its own stored data through integrated sensing circuitry, without requiring external processing resources. This self-service capability allows the memory to execute logical operations in-place, reducing energy consumption associated with data movement and improving overall processing efficiency.
2Ease of operation
If external processing resources are used to perform logical operations, then complex operations can be executed, but the need for data transfer increases processing time and power consumption
Solution Approach 1:
By merging processing capabilities directly into the memory array through sensing circuitry, the system eliminates time-consuming data transfer operations. The sensing circuitry performs logical operations in-place on stored data, significantly reducing processing time while maintaining operational simplicity through integrated control.
3Productivity
If more temporary storage rows are used for processing operations, then more data can be processed in parallel, but memory density decreases
Solution Approach 1:
The patent merges processing and storage functions by implementing sensing circuitry that performs logical operations directly on data within the memory array. This eliminates the need for separate temporary storage rows, allowing parallel processing without compromising memory density.
Solution Approach 2:
The sensing circuitry serves multiple functions: it performs read operations, performs logical operations (AND, OR, XOR, etc.), and stores results back in the same memory array. This multi-functionality enables parallel processing without requiring additional dedicated storage resources, thereby maintaining high memory density.
4Productivity
If sensing circuitry performs operations within the memory array, then data transfer is minimized, but the complexity of the memory device increases
Solution Approach 1:
The patent combines sensing and processing functions into a single integrated sensing circuitry block within the memory array. This merging approach improves processing efficiency by eliminating data transfer while managing complexity through functional integration rather than separate components.
Solution Approach 2:
The sensing circuitry is designed to perform multiple logical operations (AND, OR, XOR, XNOR, etc.) and data manipulation tasks within a single integrated structure. This multi-functionality approach improves processing efficiency while controlling device complexity by avoiding the need for separate dedicated circuits for each operation.
Data Source
AI summary
Examples of the present disclosure provide apparatuses and methods for performing signed element compare operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to perform a number of operations to compare a value of a first signed element stored in the first group of memory cells to a value of a second signed element stored in the second group of memory cells.